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4 MOSEL VITELIC V436516S04VATG-75PC V436516S04VATG-75PC Rev. 1.4 September 2001 Serial Presence Detect Information A serial presence detect storage device - E2PROM - is assembled onto the module. Informa- tion about the module configuration, speed, etc. is writtenintothe E2PROM device during module pro- duction using a serial presence detect protocol (I2C synchronous 2-wire bus) SPD-Table for PC133 modules: Byte Number Function Described SPD Entry Value Hex Value 16Mx64 0 Number of SPD bytes 128 80 1 Total bytes in Serial PD 256 08 2 Memory Type SDRAM 04 3 Number of Row Addresses (without BS bits) 12 0C 4 Number of Column Addresses (for x8 SDRAM) 10 0A 5 Number of DIMM Banks 1 01 6 Module Data Width 64 40 7 Module Data Width (continued) 0 00 8 Module Interface Levels LVTTL 01 9 SDRAM Cycle Time at CL=3 7.5 ns 75 10 SDRAM Access Time from Clock at CL=3 5.4 ns 54 11 Dimm Config (Error Det/Corr.) none 00 12 Refresh Rate/Type Self-Refresh, 15.6 µs80 13 SDRAM width, Primary x8 08 14 Error CheckingSDRAMDataWidth n/a/ x8 00 15 Minimum Clock Delay from Back to Back Random Column Address tccd =1CLK 01 16 Burst Length Supported 1, 2, 4, 8 0F 17 Number of SDRAM Banks 4 04 18 Supported CAS Latencies CL = 3, 2 06 19 CS Latencies CS Latency = 0 01 20 WE Latencies WL = 0 01 21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00 22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 23 MinimumClock CycleTimeat CAS Latency = 2 7.5 ns 75 24 Maximum Data Access Time from Clock for CL = 2 5.4 ns 54 25 Minimum Clock Cycle Time at CL = 1 Not Supported 00 26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00 27 Minimum Row Precharge Time 15 ns 0F 28 Minimum Row Active to Row Active Delay tRRD 14 ns 0E 29 Minimum RAS to CAS Delay tRCD 15 ns 0F 30 Minimum RAS Pulse Width tRAS 42 ns 2A |
