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MOSEL VITELIC V436516S04VATG-75 5 V436516S04VATG-75 Rev. 2.0 July 2001 DC Characteristics TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V 31 Module Bank Density (Per Bank) 128 MByte 20 32 SDRAM Input Setup Time 1.5 ns 15 33 SDRAM Input Hold Time 0.8 ns 08 34 SDRAM Data Input Setup Time 1.5 ns 15 35 SDRAM Data Input Hold Time 0.8 ns 08 62-61 Superset Information (May be used in Future) 00 62 SPD Revision Revision 2.0 02 63 Checksum for Bytes 0 - 62 1D 64 Manufacturer’s JEDEC ID Code Mosel Vitelic 40 65-71 Manufacturer’s JEDEC ID Code (cont.) 00 72 Manufacturing Location 73-90 Module Part Number (ASCII) V436516S04VATG-75 91-92 PCB Identification Code 93 Assembly Manufacturing Date (Year) 94 Assembly Manufacturing Date (Week) 95-98 Assembly Serial Number 99-125 Reserved 00 126 Intel Specification for Frequency 64 127 Reserved AD 128+ Unused Storage Location 00 Symbol Parameter Limit Values Unit Min. Max. VIH Input High Voltage 2.0 VCC+0.3 V VIL Input Low Voltage –0.5 0.8 V VOH Output High Voltage (IOUT = –2.0 mA) 2.4 — V VOL Output Low Voltage (IOUT = 2.0 mA) — 0.4 V II(L) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) –40 40 µA IO(L) Output leakage current (DQ is disabled, 0V < VOUT < VCC) –40 40 µA SPD-Table for PC133 modules: (Continued) Byte Number Function Described SPD Entry Value Hex Value 16Mx64 |
