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1

2

3

11

12

14

15

CS

SCLK

SDO

0

0

D9

D8

D0

0

0

13

0

0

16

b

a

a

ADS7885 NORMAL OPERATION

1

2

3

9

10

14

15

CS

SCLK

SDO

0

0

D7

D6

D0

0

0

11

0

0

16

b

a

a

0

POWER DOWN MODE

ADS7884

ADS7885

SLAS567 – MARCH 2008

Figure 1. ADS7884 Interface Timing Diagram

The cycle begins with the falling edge of CS . This point is indicated as a in Figure 2. With the falling edge of CS,

the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion

is in progress. The data word contains 2 leading zeros, followed by 8-bit data in MSB first format and padded by

6 lagging zeros.

The falling edge of CS clocks out the first zero, and a second zero is clocked out on FIRST falling edge of the

clock. Data is in MSB first format with the MSB being clocked out on the 3rd falling edge. Data is padded with six

lagging zeros as shown in Figure 2. On the 16th falling edge of SCLK, SDO goes to the 3-state condition. The

conversion ends on the first rising edge of SCLK after the 9th falling edge. At this point the device enters the

acquisition phase. This point is indicated by b in Figure 2.

Figure 2 shows device data is read in a sixteen clock frame. However, CS can be asserted (pulled high) any time

after 9 clocks have elapsed (after the 10th falling edge of SCLK). SDO goes to 3-state with the CS high level.

necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase

and no valid data is available in the next cycle. (Also refer to the Powerdown Mode section for more details.) CS

going high any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.

high as 5.5 V when the device supply is 2.7 V. This feature is useful when digital signals are coming from

another circuit with different supply levels. Also, this relaxes the restriction on powerup sequencing. However, the

Figure 2. ADS7885 Interface Timing Diagram

The device enters powerdown mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10th

SCLK falling edge. Ongoing conversion stops and SDO goes to 3-state under this powerdown condition as

shown in Figure 3.

8

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