 |
 |
|
| TMS320DM6443_08 |
|
|||||||||||||||||
 TI
|
| |||||||||||||||||
|
5 page 
1.3 Functional Block Diagram JTAG Interface System Control PLLs/Clock Generator Input Clock(s) Power/Sleep Controller Pin Multiplexing ARM Subsystem ARM926EJ-S CPU 16 KB I-Cache 16 KB RAM 8 KB D-Cache 8 KB ROM DSP Subsystem C64x+ t DSP CPU 32 KB L1 Pgm 64 KB L2 RAM 80 KB L1 Data BT.656, Y/C, Raw (Bayer) Video Processing Subsystem (VPSS) CCD Controller Video Interface Front End Resizer Histogram/ 3A Preview 10b DAC On-Screen Display (OSD) Video Encoder (VENC) 10b DAC 10b DAC 10b DAC Back End 8b BT.656, Y/C, 24b RGB NTSC/ PAL, S-Video, RGB, YPbPr Switched Central Resource (SCR) Peripherals EDMA Audio Serial Port I2C SPI UART Serial Interfaces DDR2 Mem Ctlr (16b/32b) Async EMIF/ NAND/ SmartMedia ATA/ Compact Flash MMC/ SD/ SDIO Program/Data Storage Watchdog Timer PWM System General- Purpose Timer USB 2.0 PHY VLYNQ EMAC With MDIO Connectivity HPI TMS320DM6443 Digital Media System-on-Chip www.ti.com SPRS282F – DECEMBER 2005 – REVISED MARCH 2008 Figure 1-1 shows the functional block diagram of the device. Figure 1-1. TMS320DM6443 Functional Block Diagram Digital Media System-on-Chip (DMSoC) 5 |
