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TMX320DM6467ZUT Datasheet(PDF) 5 Page - Texas Instruments |
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TMX320DM6467ZUT Datasheet(HTML) 5 Page - Texas Instruments |
5 / 340 page 1.3 Functional Block Diagram JTAG Interface System Control PLLs/Clock Generator Input Clock(s) Power/Sleep Controller Pin Multiplexing ARM Subsystem ARM926EJ-S CPU 16 KB I-Cache 32 KB RAM 8 KB D-Cache 8 KB ROM DSP Subsystem C64x+ t DSP CPU 32 KB L1 Pgm 128 KB L2 RAM 32 KB L1 Data High Definition Video-Imaging Coprocessor (HDVICP0) Switched Central Resource (SCR) Peripherals EDMA I2C SPI UART Serial Interfaces DDR2 Mem Ctlr (16b/32b) Async EMIF/ NAND/ SmartMedia ATA Program/Data Storage Watchdog Timer PWM System General- Purpose Timer USB 2.0 PHY VLYNQ EMAC With MDIO Connectivity HPI McASP Video Port I/F PCI (33 MHz) TSIF High Definition Video-Imaging Coprocessor (HDVICP1) CRGEN VDCE TMS320DM6467 Digital Media System-on-Chip www.ti.com SPRS403A – DECEMBER 2007 – REVISED MAY 2008 Figure 1-1 shows the functional block diagram of the device. Figure 1-1. TMS320DM6467 Functional Block Diagram Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) 5 |
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