M59DR032C100ZB1T datasheet(6/38 Pages) STMICROELECTRONICS

Part #	M59DR032C100ZB1T

Description	32 Mbit 2Mb x16, Dual Bank, Page Low Voltage Flash Memory

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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M59DR032A, M59DR032B

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SIGNAL DESCRIPTIONS

See Figure 1 and Table 1.

Address Inputs (A0-A20). The address inputs

for the memory array are latched during a write op-

eration on the falling edge of Chip Enable E or

Write Enable W, whichever occurs last.

Data Input/Output (DQ0-DQ15). The

Input

is

data to be programmed in the memory array or a

command to be written to the Command Interface

(C.I.) Both input data and commands are latched

on the rising edge of Write Enable W. The Ouput

is data from the Memory Array, the Common Flash

Interface, the Electronic Signature Manufacturer

or Device codes, the Block Protection status, the

Configuration Register status or the Status Regis-

ter Data Polling bit DQ7, the Toggle Bits DQ6 and

DQ2, the Error bit DQ5. The data bus is high im-

pedance when the chip is deselected, Output En-

able G is at VIH, or RP is at VIL.

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. E at VIH deselects

the memory and reduces the power consumption

to the standby level. E can also be used to control

writing to the command register and to the memo-

ry array, while W remains at VIL.

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read op-

eration. When G is at VIH the outputs are High im-

pedance.

Write Enable (W). This input controls writing to

the Command Register and Data latches. Data are

latched on the rising edge of W.

Write Protect (WP). This input gives an addition-

al hardware protection level against program or

erase when pulled at VIL, as described in the Block

Lock instruction description.

Reset/Power Down Input (RP). The

RP

input

provides hardware reset of the memory (without

affecting the Configuration Register status), and/

or Power Down functions, depending on the Con-

figuration Register status. Reset/Power Down of

the memory is achieved by pulling RP to VIL for at

least tPLPH. When the reset pulse is given, if the

memory is in Read, Erase Suspend Read or

Standby, it will output new valid data in tPHQ7V1 af-

ter the rising edge of RP. If the memory is in Erase

or Program modes, the operation will be aborted

and the reset recovery will take a maximum ot

tPLQ7V. The memory will recover from Power

Down (when enabled) in tPHQ7V2 after the rising

edge of RP. See Tables 25, 26 and Figure 9.

VDD and VDDQ Supply Voltage (1.65V to 2.2V).

The main power supply for all operations (Read,

Program and Erase). VDD and VDDQ must be at

the same voltage.

VPP Programming Voltage (11.4V to 12.6V). Used

to provide high voltage for fast factory program-

ming. High voltage on VPP pin is required to use

the Double Word Program instruction. It is also

possible to perform word program or erase instruc-

tions with VPP pin grounded.

VSS Ground. VSS is the reference for all the volt-

age measurements.

DEVICE OPERATIONS

The following operations can be performed using

the appropriate bus cycles: Read Array (Random,

and Page Modes), Write command, Output Dis-

able, Standby, Reset/Power Down and Block

Locking. See Table 8.

Read. Read operations are used to output the

contents of the Memory Array, the Electronic Sig-

nature, the Status Register, the CFI, the Block

Protection Status or the Configuration Register

status. Read operation of the memory array is per-

formed in asynchronous page mode, that provides

fast access time. Data is internally read and stored

in a page buffer. The page has a size of 4 words

and is addressed by A0-A1 address inputs. Read

operations of the Electronic Signature, the Status

Register, the CFI, the Block Protection Status, the

Configuration Register status and the Security

Code are performed as single asyncronous read

cycles (Random Read). Both Chip Enable E and

Output Enable G must be at VIL in order to read the

output of the memory.

Write. Write operations are used to give Instruc-

tion Commands to the memory or to latch Input

Data to be programmed. A write operation is initi-

ated when Chip Enable E and Write Enable W are

at VIL with Output Enable G at VIH. Addresses are

latched on the falling edge of W or E whichever oc-

curs last. Commands and Input Data are latched

on the rising edge of W or E whichever occurs first.

Noise pulses of less than 5ns typical on E, W and

G signals do not start a write cycle.

Table 7. Bank Size and Sectorization

Bank Size

Parameter Blocks

Main Blocks

Bank A

4 Mbit

8 blocks of 4 KWord

7 blocks of 32 KWord

Bank B

28 Mbit

-

56 blocks of 32 KWord

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