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ISO7231A Datasheet(PDF) 6 Page - Texas Instruments |
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ISO7231A Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 17 page  ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V (1) OPERATION SWITCHING CHARACTERISTICS: VCC1 at 3.3-V and VCC2 at 5-V OPERATION ISO7230A ISO7231A SLLS906 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT Quiescent 0.5 1 ISO7230A VI = VCC or 0 V, All channels, no load, EN2 at 3 V mA 1 Mbps 1 2 ICC1 Quiescent 4.5 7 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, ISO7231A mA EN2 at 3 V 1 Mbps 4.5 7 Quiescent 15 22 ISO7230A VI = VCC or 0 V, All channels, no load, EN2 at 3 V mA 1 Mbps 16 22 ICC2 Quiescent 13 20 VI = VCC or 0 V, All channels, no load, EN1 at 3 V, ISO7231A mA EN2 at 3 V 1 Mbps 13 20 ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current EN at VCC, Single channel 0 µA IOH = –4 mA, See Figure 1 ISO7230 VCC – 0.4 ISO7231 VOH High-level output voltage VCC – 0.8 V (5-V side) IOH = –20 µA, See Figure 1 VCC – 0.1 IOL = 4 mA, See Figure 1 0.4 VOL Low-level output voltage V IOL = 20 µA, See Figure 1 0.1 VI(HYS) Input voltage hysteresis 150 mV IIH High-level input current 10 IN from 0 V to VCC µA IIL Low-level input current –10 CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) 2 pF Common-mode transient VI = VCC or 0 V, See Figure 4 CMTI 25 50 kV/ µs immunity (1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V. , over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH, tPHL Propagation delay 40 100 ISO723xA See Figure 1 ns PWD Pulse-width distortion(1) |tPHL – tPLH| 11 tsk(o) Channel-to-channel output skew (2) ISO723xA 0 2.5 ns tr Output signal rise time 2 See Figure 1 ns tf Output signal fall time 2 tPHZ Propagation delay, high-level-to-high-impedance output 15 20 tPZH Propagation delay, high-impedance-to-high-level output 15 20 See Figure 2 ns tPLZ Propagation delay, low-level-to-high-impedance output 15 20 tPZL Propagation delay, high-impedance-to-low-level output 15 20 tfs Failsafe output delay time from input power loss See Figure 3 12 µs (1) Also known as pulse skew (2) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ISO7230A ISO7231A |
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