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M68AW127BL10MC1T Datasheet(PDF) 8 Page - STMicroelectronics |
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M68AW127BL10MC1T Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 20 page  M68AW127B 8/20 OPERATION The M68AW127B has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E1 = High), or Chip Select is asserted (E2 = Low). An Output Enable (G) signal provides a high-speed, tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Opera- tional modes are determined by device control in- puts W and E1 as summarized in the Operating Modes table (Table 6). Table 6. Operating Modes Note: X = VIH or VIL. Read Mode The M68AW127B is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, Chip Enable (E1) is asserted and Chip Select (E2) is de-asserted. This provides access to data from eight of the 1,048,576 locations in the static memory array, specified by the 17 address inputs. Valid data will be available at the eight output pins within tAVQV after the last stable address, provid- ing G is Low and E1 is Low. If Chip Enable or Out- put Enable access times are not met, data access will be measured from the limiting parameter (tELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX, but data lines will always be valid at tAVQV. Figure 8. Address Controlled, Read Mode AC Waveforms Note: E1 = Low, E2 = High, G = Low, W = High. Operation E1 E2 W G DQ0-DQ7 Power Read VIL VIH VIH VIH Hi-Z Active (ICC) Read VIL VIH VIH VIL Data Output Active (ICC) Write VIL VIH VIL X Data Input Active (ICC) Deselect VIH X X X Hi-Z Standby (ISB) Deselect X VIL X X Hi-Z Standby (ISB) AI05474 tAVAV tAVQV tAXQX A0-A16 DQ0-DQ7 VALID DATA VALID |
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