M58LW032D110N1F datasheet(10/51 Pages) STMICROELECTRONICS

Part #	M58LW032D110N1F

Description	32 Mbit 4Mb x8, 2Mb x16, Uniform Block 3V Supply Flash Memory

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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M58LW032D

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SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Input (A0). The A0 address input is

used to select the higher or lower Byte in X8 mode.

It is not used in X16 mode (where A1 is the Lowest

Significant bit).

Address Inputs (A1-A21). The Address Inputs

are used to select the cells to access in the mem-

ory array during Bus Read operations either to

read or to program data to. During Bus Write oper-

ations they control the commands sent to the

Command Interface of the Program/Erase Con-

troller.

The device must be enabled (refer to Table 2, De-

vice Enable) when selecting the addresses. The

address inputs are latched on the rising edge of

Write Enable or on the first edge of Chip Enables

E0, E1 or E2 that disable the device, whichever

occurs first.

Data Inputs/Outputs (DQ0-DQ15). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation, or are used

to input the data during a program operation. Dur-

ing Bus Write operations they represent the com-

mands sent to the Command Interface of the

Program/Erase Controller. When used to input

data or Write commands they are latched on the

rising edge of Write Enable or the first edge of

Chip Enables E0, E1 or E2 that disable the device,

whichever occurs first.

When the device is enabled and Output Enable is

low, VIL (refer to Table 2, Device Enable), the data

bus outputs data from the memory array, the Elec-

tronic Signature, the Block Protection status, the

CFI Information or the contents of the Status Reg-

ister. The data bus is high impedance when the

device is deselected, Output Enable is high, VIH, or

the Reset/Power-Down signal is low, VIL. When

the Program/Erase Controller is active the Ready/

Busy status is given on DQ7.

Chip Enables (E0, E1, E2). The Chip Enable in-

puts E0, E1 and E2 activate the memory control

logic, input buffers, decoders and sense amplifi-

ers. The device is selected at the first edge of Chip

Enables E0, E1 or E2 that enable the device and

deselected at the first edge of Chip Enables E0,

E1 or E2 that disable the device. Refer to Table 2,

Device Enable for more details.

When the Chip Enable inputs deselect the memo-

ry, power consumption is reduced to the Standby

level, IDD1.

Output Enable (G). The Output Enable, G, gates

the outputs through the data output buffers during

a read operation. When Output Enable, G, is at VIH

the outputs are high impedance.

Write Enable (W). The Write Enable input, W,

controls writing to the Command Interface, Input

Address and Data latches. Both addresses and

data can be latched on the rising edge of Write En-

able.

Reset/Power-Down (RP). The

Reset/Power-

Down pin can be used to apply a Hardware Reset

to the memory.

A Hardware Reset is achieved by holding Reset/

Power-Down Low, VIL, for at least tPLPH. When

Reset/Power-Down is Low, VIL, the Status Regis-

ter information is cleared and the power consump-

tion is reduced to power-down level. The device is

deselected and outputs are high impedance. If Re-

set/Power-Down goes low, VIL,during a Block

Erase, a Write to Buffer and Program or a Block

Protect/Unprotect the operation is aborted and the

data may be corrupted. In this case the STS pin

stays low, VIL, for a maximum timing of tPLPH + tPH-

BH, until the completion of the Reset/Power-Down

pulse.

After Reset/Power-Down goes High, VIH, the

memory will be ready for Bus Read and Bus Write

operations after tPHQV. Note that STS does not fall

during a reset, see Ready/Busy Output section.

In an application, it is recommended to associate

Reset/Power-Down pin, RP, with the reset signal

of the microprocessor. Otherwise, if a reset opera-

tion occurs while the memory is performing an

Erase or Program operation, the memory may out-

put the Status Register information instead of be-

ing

initialized

to

the

default

Asynchronous

Random Read.

Byte/Word Organization Select (BYTE). The

Byte/Word Organization Select pin is used to

switch between the x8 and x16 bus widths of the

memory. When Byte/Word Organization Select is

Low, VIL, the memory is in x8 mode, when it is

High, VIH, the memory is in x16 mode.

Status/(Ready/Busy) (STS). The STS signal is

an open drain output that can be used to identify

the Program/Erase Controller status. It can be

configured in two modes:

s

Ready/Busy - the pin is Low, VOL, during

Program and Erase operations and high

impedance when the memory is ready for any

Read, Program or Erase operation.

s

Status - the pin gives a pulsing signal to indicate

the end of a Program or Block Erase operation.

After power-up or reset the STS pin is configured

in Ready/Busy mode. The pin can be configured

for Status mode using the Configure STS com-

mand.

When the Program/Erase Controller is idle, or sus-

pended, STS can float High through a pull-up re-

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