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STM32F103ZD Datasheet(PDF) 6 Page - STMicroelectronics |
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STM32F103ZD Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 118 page List of figures STM32F103xC, STM32F103xD, STM32F103xE 6/118 List of figures Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . 19 Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 3. STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP144 pinout. . 21 Figure 4. STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP100 pinout. . 22 Figure 5. STM32F103xC, STM32F103xD and STM32F103xE performance line LQFP64 pinout. . . 23 Figure 6. STM32F103xC, STM32F103xD and STM32F103xE performance line BGA100 ballout . . 24 Figure 7. STM32F103xC, STM32F103xD and STM32F103xE performance line BGA144 ballout . . 25 Figure 8. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 42 Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 42 Figure 15. Current consumption in Stop mode with regulator in main mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 16. Current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 17. Current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 19. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 20. Typical application with a 8-MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 21. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 22. Asynchronous non-multiplexed SRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 23. Asynchronous non-multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 24. Asynchronous multiplexed SRAM/NOR write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 25. Asynchronous multiplexed SRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 26. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 27. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 28. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 29. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 30. PC-card controller timing for common memory read access . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 31. PC-card controller timing for common memory write access . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 32. PC-card controller timing for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 33. PC-card controller timing for attribute memory write access . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 34. PC-card controller timing for I/O space read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 35. PC-card controller timing for I/O space write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 36. NAND controller timing for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 37. NAND controller timing for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 38. NAND controller timing for common memory read access . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 39. NAND controller timing for common memory write access. . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 40. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 41. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 42. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 43. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 |
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