M59DR008E100ZB1T datasheet(8/37 Pages) STMICROELECTRONICS

Part #	M59DR008E100ZB1T

Description	8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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Auto Select (AS) Instruction. This

instruction

uses two Coded Cycles followed by one write cy-

cle giving the command 90h to address 555h for

command set-up. A subsequent read will output

the Manufacturer or the Device Code (Electronic

Signature), the Block Protection status or the Con-

figuration Register status depending on the levels

of A0 and A1 (see Tables 9, 10 and 11). A7-A2

must be at VIL, while other address input are ig-

nored. The bank address is don’t care for this in-

struction. The Electronic Signature can be read

from the memory allowing programming equip-

ment or applications to automatically match their

interface to the characteristics of M59DR008. The

Manufacturer Code is output when the address

lines A0 and A1 are at VIL, the Device Code is out-

put when A0 is at VIH with A1 at VIL.

The codes are output on DQ0-DQ7 with DQ8-

DQ15 at 00h. The AS instruction also allows the

access to the Block Protection Status. After giving

the AS instruction, A0 is set to VIL with A1 at VIH,

while A12-A18 define the address of the block to

be verified. A read in these conditions will output a

01h if the block is protected and a 00h if the block

is not protected.

The AS Instruction finally allows the access to the

Configuration Register status if both A0 and A1

are set to VIH. If DQ10 is '0' only the Reset function

is active as RP is set to VIL (default at power-up).

If DQ10 is '1' both the Reset and the Power Down

functions will be achieved by pulling RP to VIL. The

other bits of the Configuration Register are re-

served and must be ignored. A reset command

puts the device in read array mode.

Write Configuration Register (CR) Instruc-

tion. This instruction uses two Coded Cycles fol-

lowed by one write cycle giving the command 60h

to address 555h. A further write cycle giving the

command 03h writes the contents of address bits

A0-A15 to the 16 bits configuration register. Bits

written by inputs A0-A9 and A11-A15 are reserved

for future use. Address input A10 defines the sta-

tus of the Reset/Power Down functions. It must be

set to VIL to enable only the Reset function and to

VIH to enable also the Power Down function. At

Power Up all the Configuration Register bits are

reset to '0'.

Enter Bypass Mode (EBY) Instruction. This in-

struction uses the two Coded cycles followed by

one write cycle giving the command 20h to ad-

dress 555h for mode set-up. Once in Bypass

mode, the device will accept the Exit Bypass

(XBY) and Program or Double Word Program in

Bypass mode (PGBY, DPGBY) commands. The

Bypass mode allows to reduce the overall pro-

gramming time when large memory arrays need to

be programmed.

Exit Bypass Mode (XBY) Instruction. This

in-

struction uses two write cycles. The first inputs to

the memory the command 90h and the second in-

puts the Exit Bypass mode confirm (00h). After the

XBY instruction, the device resets to Read Memo-

ry Array mode.

Program in Bypass Mode (PGBY) Instruc-

tion. This instruction uses two write cycles. The

Program command A0h is written to any Address

on the first cycle and the second write cycle latch-

es the Address on the falling edge of W or E and

the Data to be written on the rising edge and starts

the P/E.C. Read operations within the same bank

output the Status Register bits after the program-

ming has started. Memory programming is made

only by writing '0' in place of '1'. Status bits DQ6

and DQ7 determine if programming is on-going

and DQ5 allows verification of any possible error.

Program (PG) Instruction. This instruction uses

four write cycles. The Program command A0h is

written to address 555h on the third cycle after two

Coded Cycles. A fourth write operation latches the

Address and the Data to be written and starts the

P/E.C. Read operations within the same bank out-

put the Status Register bits after the programming

has started. Memory programming is made only

by writing '0' in place of '1'. Status bits DQ6 and

DQ7 determine if programming is on-going and

DQ5 allows verification of any possible error. Pro-

gramming at an address not in blocks being

erased is also possible during erase suspend.

Double Word Program (DPG) Instruction. This

feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel. High voltage (11.4V to 12.6V) on VPP

pin is required. This instruction uses five write cy-

cles. The double word program command 40h is

written to address 555h on the third cycle after two

Coded Cycles. A fourth write cycle latches the ad-

dress and data to be written to the first location. A

fifth write cycle latches the new data to be written

to the second location and starts the P/E.C.. Note

that the two locations must have the same address

except for the address bit A0. The Double Word

Program can be executed in Bypass mode (DPG-

BY) to skip the two coded cycles at the beginning

of each command.

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