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M68Z128-55N1 Datasheet(PDF) 3 Page - STMicroelectronics |
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M68Z128-55N1 Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 12 page 3/12 M68Z128 falling edge of E2, whichever occurs first, and re- main valid for tWHDX, tE1HDX or tE2LDX. OPERATIONAL MODE The M68Z128 has a Chip Enable power down fea- ture which invokes an automatic standby mode whenever either Chip Enable is de-asserted (E1 = High or E2 = Low). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the com- mon I/O data bus. Operational modes are deter- mined by device control inputs W, E1, and E2 as summarized in the Operating Modes table. Table 3. Operating Modes Note: 1. X = VIH or VIL. Operation E1 E2 W G DQ0-DQ7 Power Read VIL VIH VIH VIH Hi-Z Active Read VIL VIH VIH VIL Data Output Active Write VIL VIH VIL X Data Input Active Deselect VIH XX X Hi-Z Standby Deselect X VIL X X Hi-Z Standby Table 4. AC Measurement Conditions Note: Output Hi-Z is defined as the point where data is no longer driven. Input Rise and Fall Times ≤ 15ns Input Pulse Voltages 0 to 3V Input and Output Timing Ref. Voltages 1.5V Figure 3. AC Testing Load Circuit AI00658B 5.0V OUT CL = 50pF or 5pF CL includes JIG capacitance 1800 Ω DEVICE UNDER TEST 990 Ω Table 5. Capacitance (1) (TA = 25 °C, f = 1 MHz) Note: 1. Sampled only, not 100% tested. 2. Outputs deselected. Symbol Parameter Test Condition Min Max Unit CIN Input Capacitance on all pins (except DQ) VIN = 0V 9pF COUT (2) Output Capacitance VOUT = 0V 9pF |
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