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M58LW064B150NH1T Datasheet(PDF) 1 Page - STMicroelectronics |
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M58LW064B150NH1T Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 53 page  1/53 PRODUCT PREVIEW May 2000 This is preliminary information on a new product now in development. Details are subject to change without notice. M58LW064A M58LW064B 64 Mbit (x16 and x16/x32, Block Erase) Low Voltage Flash Memories s M58LW064A x16 organisation, s M58LW064B x16/x32 selectable s MULTI-BIT CELL for HIGH DENSITY and LOW COST s SUPPLY VOLTAGE –VDD = 2.7V to 3.6V Supply Voltage –VDDQ = 2.7V to 3.6V or 1.8V to 2.5V Input/Output Supply Voltage s PIPELINED SYNCHRONOUS BURST INTERFACE s SYNCHRONOUS/ASYNCHRONOUS READ – Synchronous Burst read – Asynchronous Random and Latch Enabled Controlled Read, with Page Read s ACCESS TIME – Synchronous Burst Read up to 66MHz – Asynchronous Page Mode Read 150/25ns, Random Read 150ns s PROGRAMMING TIME – 16 Word or 8 Double-Word Write Buffer – 12us Word effective programming time s MEMORY BLOCKS – 64 Equal blocks of 1 Mbit s ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code M58LW064A: 17h – Device Code M58LW064B: 14h DESCRIPTION The M58LW064 is a non-volatile Flash memory that may be erased electrically at the block level and programmed in-system on a 16 Word or 8 Double-Word basis using a 2.7V to 3.6V supply for the circuit and a supply down to 1.8V for the Input and Output buffers. The M58LW064A is organised as 4M by 16 bit. The M58LW064B has 4M by 16 bit or 2M by 32 bit organisation selectable by the Word Organisation WORD input. Both devices are internally configured as 64 blocks of 1 Mbit each. FBGA 86 1 TSOP56 (NF) LBGA54 (ZA) PQFP80 (T) TSOP86 II (NH) Figure 1. Logic Diagram Note: 1. Only on M58LW064B. AI03223 22 A1-A22 W DQ0-DQ31 VDD M58LW064A M58LW064B E VSS 32 G RP L VDDQ B K RB R VPP WORD (1) |
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