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HA-2556 Datasheet(PDF) 5 Page - Intersil Corporation |
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HA-2556 Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 18 page  5 FN2477.6 April 29, 2008 Simplified Schematic Application Information Operation at Reduced Supply Voltages The HA-2556 will operate over a range of supply voltages, ±5V to ±15V. Use of supply voltages below ±12V will reduce input and output voltage ranges. See “Typical Performance Curves” on page 12 for more information. Offset Adjustment X-Channel and Y-Channel offset voltages may be nulled by using a 20k potentiometer between the VYIO or VXIO adjust pin A and B and connecting the wiper to V-. Reducing the channel offset voltage, will reduce AC feedthrough and improve the multiplication error. Output offset voltage can also be nulled by connecting VZ- to the wiper of a potentiometer which is tied between V+ and V-. Capacitive Drive Capability When driving capacitive loads >20pF a 50 Ω resistor should be connected between VOUT and VZ+, using VZ+ as the output (see Figure 1). This will prevent the multiplier from going unstable and reduce gain peaking at high frequencies. The 50 Ω resistor will dampen the resonance formed with the capacitive load and the inductance of the output at Pin 8. Gain accuracy will be maintained because the resistor is inside the feedback loop. Theory of Operation The HA-2556 creates an output voltage that is the product of the X and Y input voltages divided by a constant scale factor of 5V. The resulting output has the correct polarity in each of the four quadrants defined by the combinations of positive and negative X and Y inputs. The Z stage provides the means for negative feedback (in the multiplier configuration) and an input for summation into the output. This results in Equation 1, where X, Y and Z are high impedance differential inputs. To accomplish this the differential input voltages are first converted into differential currents by the X and Y input transconductance stages. The currents are then scaled by a constant reference and combined in the multiplier core. The multiplier core is a basic Gilbert Cell that produces a differential output current proportional to the product of X and Y input signal currents. This current becomes the output for the HA-2557. The HA-2556 takes the output current of the core and feeds it to a transimpedance amplifier, that converts the current to a voltage. In the multiplier configuration, negative feedback is provided with the Z transconductance amplifier by connecting VOUT to the Z input. The Z stage converts VOUT to a current which is subtracted from the multiplier core before being applied to the high gain transimpedance amp. The Z stage, by virtue of it’s similarity to the X and Y stages, also cancels VBIAS OUT VZ- VCC VZ+ V- V+ VYIOA VYIOB VY- VY+ VXIOAVXIOB VX+ REF GND VX- + - VBIAS NC NC VY+ -15V VOUT +15V VX+ NC NC 50 Ω 1k Ω 20pF NC NC VZ- VZ+ 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 Σ + - REF + - + - + - FIGURE 1. DRIVING CAPACITIVE LOAD V OUT = Z X x Y 5 -------------- = (EQ. 1) HA-2556 |
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Similar Description - HA-2556 |
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