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M58MR032D100ZC6T Datasheet(PDF) 5 Page - STMicroelectronics |
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M58MR032D100ZC6T Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 52 page  5/52 M58MR032C, M58MR032D SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs or Data Input/Output (ADQ0- ADQ15). When Chip Enable E is at VIL and Out- put Enable G is at VIH the multiplexed address/ data bus is used to input addresses for the memo- ry array, data to be programmed in the memory ar- ray or commands to be written to the C.I. The address inputs for the memory array are latched on the rising edge of Latch Enable L. The address latch is transparent when L is at VIL. In synchro- nous operations the address is also latched on the first rising/falling edge of K (depending on clock configuration) when L is low. Both input data and commands are latched on the rising edge of Write Enable W. When Chip Enable E and Output En- able G are at VIL the address/data bus outputs data from the Memory Array, the Electronic Signa- ture Manufacturer or Device codes, the Block Pro- tection status the Read Configuration Register status, the protection register or the Status Regis- ter. The address/data bus is high impedance when the chip is deselected, Output Enable G is at VIH, or RP is at VIL. Address Inputs (A16-A20). The five MSB ad- dresses of the memory array are latched on the rising edge of Latch Enable L. In synchronous op- eration these inputs are also latched on the first rising/falling edge of K (depending on clock config- uration) when L is low. Chip Enable (E). The Chip Enable input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. E at VIH deselects the memory and reduces the power consumption to the standby level. E can also be used to control writing to the command register and to the memo- ry array, while W remains at VIL. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read op- eration. When G is at VIH the outputs are High im- pedance. Write Enable (W). This input controls writing to the Command Register and Data latches. Data are latched on the rising edge of W. Write Protect (WP). This input gives an addition- al hardware protection level against program or erase when pulled at VIL, as described in the Block Lock instruction description. Reset/Power-down Input (RP). The RP input provides hardware reset of the memory, and/or Power-down functions, depending on the Read Configuration Register status. Reset/Power-down of the memory is achieved by pulling RP to VIL for at least tPLPH. When the reset pulse is given, the memory will recover from Power-down (when en- abled) in a minimum of tPHEL, tPHLL or tPHWL (see Table 31 and Figure 15) after the rising edge of RP. Exit from Reset/Power-down changes the contents of the Read Configuration Register bits 14 and 15, setting the memory in asynchronous page mode read and power save function dis- abled. All blocks are protected and unlocked after a Reset/Power-down. Latch Enable (L). L latches the address bits ADQ0-ADQ15 and A16-A20 on its rising edge. The address latch is transparent when L is at VIL and it is inhibited when L is at VIH. Clock (K). The clock input synchronizes the memory to the micro controller during burst mode read operation; the address is latched on a K edge (rising or falling, according to the configuration set- tings) when L is at VIL. K is don’t care during asyn- chronous page mode read and in write operations. Wait (WAIT). WAIT is an output signal used dur- ing burst mode read, indicating whether the data on the output bus are valid or a wait state must be inserted. This output is high impedance when E or G are high or RP is at VIL, and can be configured to be active during the wait cycle or one clock cy- cle in advance. Bus Invert (BINV). BINV is an input/output signal used to reduce the amount of power needed to switch the external address/data bus. The power saving is achieved by inverting the data output on ADQ0-ADQ15 every time this gives an advantage in terms of number of toggling bits. In burst mode read, each new data output from the memory is compared with the previous data. If the number of transitions required on the data bus is in excess of 8, the data is inverted and the BINV signal will be driven by the memory at VOH to inform the receiv- ing system that data must be inverted before any further processing. By doing so, the actual transi- tions on the data bus will be less than 8. In a similar way, when a command is given, BINV may be driven by the system at VIH to inform the memory that the data input must be inverted. Like the other input/output pins, BINV is high im- pedance when the chip is deselected, output en- able G is at VIH or RP is at VIL; when used as an input, BINV must follow the same set-up and hold timings of the data inputs. VDD and VDDQ Supply Voltage (1.7V to 2.0V). VDD is the main power supply for all operations (Read, Program and Erase). VDDQ is the supply voltage for Input and Output. |
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