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ZL50112GAG2 Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc |
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ZL50112GAG2 Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc |
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1 / 112 page  1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2008, Zarlink Semiconductor Inc. All Rights Reserved. Features General • Circuit Emulation Services over Packet (CESoP) transport for MPLS, IP and Ethernet networks • On chip timing & synchronization recovery across a packet network • Grooming capability for Nx64 Kbps trunking Circuit Emulation Services • Supports ITU-T Recommendation Y.1413 and Y.1453 • Supports IETF RFC4553 and RFC5086 • Supports MEF8 and MFA 8.0.0 • Structured, synchronous CESoP with clock recovery • Unstructured, asynchronous CESoP, with integral per stream clock recovery TDM Interfaces • Up to 32 T1/E1, 8 J2, or 2 T3/E3 ports • H.110, H-MVIP, ST-BUS backplanes • Up to 1024 bi-directional 64 Kbps channels • Direct connection to LIUs, framers, backplanes • Dual reference Stratum 4 and 4E DPLL for synchronous operation Network Interfaces • Up to 3 x 100 Mbps MII Fast Ethernet or Dual Redundant 1000 Mbps GMII/TBI Ethernet Interfaces System Interfaces • Flexible 32 bit host CPU interface (Motorola PowerQUICC™ compatible) • On-chip packet memory for self-contained operation, with buffer depths of over 16 ms • Up to 8 Mbytes of off-chip packet memory, supporting buffer depths of over 128 ms April 2008 Ordering Information ZL50110GAG 552 PBGA Trays, Bake & Drypack ZL50111GAG 552 PBGA Trays, Bake & Drypack ZL50112GAG 552 PBGA Trays, Bake & Drypack ZL50114GAG 552 PBGA Trays, Bake & Drypack ZL50110GAG2 552 PBGA** Trays, Bake & Drypack ZL50111GAG2 552 PBGA** Trays, Bake & Drypack ZL50112GAG2 552 PBGA** Trays, Bake & Drypack ZL50114GAG2 552 PBGA** Trays, Bake & Drypack **Pb Fee Tin Silver/Copper -40°C to +85°C ZL50110/11/12/14 128, 256, 512 and 1024 Channel CESoP Processors Data Sheet Figure 1 - ZL50111 High Level Overview On C h ip P a c k e t M e m o ry (J itte r B u ffe r C o m p ens ation fo r 16-12 8 m s of P a c k et D e la y V a riation) Du a l Re fe re n c e Stra tu m 3 D P L L H o s t P roc es s o r In te rfa c e E x te rnal M e m o ry In te rfac e (optio n a l) 32-bit M o to ro la c o m p atib le D M A fo r s ignalin g pa c k e ts M u lti-P ro to c o l Pa c k e t P roc es s ing En g in e PW , RT P , UDP , IP v4 , IP v6 , M P L S , EC ID , VL AN , U s e r D e fined, O th e rs T rip le Pa c k e t In te rfa c e MA C (M II, G M II, T B I) TD M In te rfa c e (L IU , F ram er, B a c k pla n e ) Pe r Po rt D C O fo r Clo c k Re c o v e ry ZBT -SR A M (0 - 8 M b y te s ) |
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