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M295V100-B120N3R Datasheet(PDF) 6 Page - STMicroelectronics |
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M295V100-B120N3R Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 30 page Ready/Busy Output (RB). Ready/Busy is an open-drainoutput and gives the internal state of the P/E.C. of the device. When RB is Low, the device is Busy with a Program or Erase operation and it will not accept any additional program or erase instructions except the Erase Suspend instruction. When RB is High, the device is ready for any Read, Program or Erase operation. The RB will also be High when the memory is put in Erase Suspend or Standby modes. Reset/Block Temporary Unprotect Input (RP). The RP Input provides hardware reset and pro- tected block(s) temporary unprotection functions. Reset of the memory is acheived by pulling RP to VIL for at least 500ns. When the reset pulse is given, if the memory is in Read or Standby modes, it will be available for new operations in 50ns after the rising edge of RP. If the memory is in Erase, Erase Suspend or Program modes the reset will take 10 µs during which the RB signal will be held at VIL. The end of the memory reset will be indicated by the rising edge of RB. A hardware reset during an Erase or Program operation will corrupt the data being programmed or the sector(s) being erased. Temporary block unprotection is made by holding RP at VID. In this condition previously protected blocks can be programmed or erased. The transi- tion of RP from VIH to VID must slower than 500ns. When RP is returned from VID to VIH all blocks temporarily unprotected will be again protected. VCC Supply Voltage. The power supply for all operations (Read, Program and Erase). VSS Ground. VSS is the reference for all voltage measurements. DEVICE OPERATIONS See Tables 4, 5 and 6. Read. Read operations are used to output the contents of the Memory Array, the Electronic Sig- nature, the Status Register or the Block Protection Status. Both Chip Enable E and Output Enable G must be low in order to read the output of the memory. Write. Write operations are used to give Instruction Commands to the memory or to latch input data to be programmed. A write operation is initiated when Chip Enable E is Low and Write Enable W is Low with Output Enable G High. Addresses are latched on the falling edge of W or E whichever occurs last. Commands and Input Data are latched on the rising edge of W or E whichever occurs first. Output Disable. The data outputs are high imped- ance when the Output Enable G is High with Write Enable W High. Standby. The memory is in standby when Chip Enable E is High and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. Automatic Standby. After 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumptionis reduced to the CMOS standby value, while outputs still drive the bus. Electronic Signature. Two codes identifying the manufacturer and the device can be read from the memory. The manufacturer’s code for STMi- croelectronics is 20h, the device code is D0h for the M29F100T (Top Boot) and D1h for the M29F100B (Bottom Boot). These codes allow programming equipment or applications to automatically match their interface to the characteristics of the M29F100. The Electronic Signature is output by a Read operation when the voltage applied to A9 is at VID and address input A1 is Low. The manufac- turer code is output when the Address input A0 is Low and the device code when this input is High. Other Address inputs are ignored. The codes are output on DQ0-DQ7. The Electronic Signature can also be read, without raising A9 to VID, by giving the memory the Instruc- tion AS. If the Byte-wide configuration is selected the codes are output on DQ0-DQ7 with DQ8-DQ14 at High impedance; if the Word-wide configuration is selected the codes are output on DQ0-DQ7 with DQ8-DQ15 at 00h. Block Protection. Each block can be separately protected against Program or Erase on program- ming equipment. Block protection provides addi- tional data security, as it disables all program or erase operations.This mode is activatedwhen both A9 and G are raised to VID and an address in the block is applied on A12-A15. The Block Protection algorithm is shown in Figure 14. Block protection is initiated on the edge of W falling to VIL. Then after a delay of 100 µs, the edge of W rising to VIH ends the protection operations. Block protection verify is achieved by bringing G, E, A0 and A6 to VIL and A1 to VIH, while W is at VIH and A9 at VID. Underthese conditions, reading the data output will yield 01h if the block defined by the inputs on A12-A15 is protected. Any attempt to program or erase a pro- tected block will be ignored by the device. 6/30 M29F100T, M29F100B |
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