Radiometrix Ltd

RMX2-433-10 Data sheet

Page 7/12

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DATA

1 Data

st

1 Data

st

2 Data

nd

2 Data

nd

CLK

LE

RMX2

Terminal name

#: t0,t5 >= 100 ns t1,t2,t6 >= 20 ns t3,t4 >= 30 ns

#: Keep the LE terminal at a low level, w hen write the data to the shift resister.

MSB

CS

LDS

FC

SW

R14

R13

R1

16

14

13

12

11

10

15

CNT=1

Invalid data

N11

N10

N9

N8

N7

N6

A1

CNT=0

LSB

Figure 5: PLL IC programming timing diagram

The PLL IC, which operates as shown in the block diagram in the manual, shifts the data to the 19-bit

shift register and then transfers it to the respective latch (counter, register) by judging the CNT control

bit value input at the end.

CLK [Clock]:

Data is shifted into the shift register on the rising edge of this clock.

LE [Load Enable]:

Data in the 19-bit shift register is transferred to respective latches on the rising

edge of the clock. The data is transferred to a latch according to the control bit

CNT value.

Data [Serial Data]:

You can perform either reference counter setup or programmable counter setup

first.

TIMING CHART

Control timing in a typical application is shown in Figure 3.

Initialisation of the radio is performed following power-up and successful reset of the controlling CPU.

The FET switches controlling the radio module systems (controlled by RXSEL and TXSEL) must be set

to inactive (pin high or floating) to avoid unwanted emissions.

The power supply to the radio module is then turned on. When the radio module is first powered, the

PLL internal registers are not yet set to meaningful values, and the VCO circuit will be unstable.

Data transmission and reception is only possible 40 ms after the first set up data is sent to the PLL.

Subsequent ‘channel change’ re-programming only takes 20 ms before data can be handled.

Changing channels must be carried out in the receive mode. If switching is performed in transmission

mode, unwanted interference will be generated.

If the module is switched to the receive mode when operating in the same channel, (a new PLL setting

to be used for transmission is set while still in receiving mode, data can be sent at 5 ms after the radio

Check that the Lock Detect signal is “high” 20 ms after the channel is changed. In some cases the Lock

Detect signal becomes unstable before the lock is correctly detected, so it is necessary to note if

processing of the signal is interrupted.

*1:

DC offset may occur due to frequency drift caused by ambient temperature change. Customers

are urged to verify operation at low temperature and nitiali their timing.

*2:

Sending ‘10101…..’ preamble just after switching to transmission mode enables smoother

operation of the data extraction circuit used by the receiver.

For 9600 bps, a preamble of ‘11001100’ is effective.

Recommended preamble length:

-10 °C -+55°C: 7 ms

-20 °C - +65 °C (for operation exceeding the above range): 15 ms