DS1844

9 of 14

5-WIRE SERIAL INTERFACE

AC ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

NOTES

Port Select Setup

30

ns

14, 21

R/ W Setup

30

ns

14, 21

Clock Frequency

DC

5

MHz

14, 15

Width of CLK Pulse

50

ns

14, 15

Data Setup Time

30

ns

14, 15

Data Hold Time

0

ns

14, 15

Progapation Delay Time High to Low

Level Clock to Output

40

ns

14, 15

RST High to Clock Input High

50

ns

14, 15

RST Low from Clock Input High

50

ns

14, 15

RST Inactive

125

ns

14, 15

CLK Rise Time, CLK Fall Time

50

ns

14, 15

NOTES:

1.

All voltages are referenced to ground.

2.

3.

4.

appropriate logic levels. Appropriate logic levels specify that logic inputs are within a 0.5-volt of

5.

After this period, the first clock pulse is generated.

6.

A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the

7.

the SCL.

8.

must then be met. This will automatically be the case if the device does not stretch the LOW

period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

is released.

9.

10.

Typical values are for ta = 25°C and nominal supply voltage.