KAD5514P-12Q48 datasheet(6/31 Pages) ETC2

Part #	KAD5514P-12Q48

Description	14-bit, 250/210/170/125MSPS A/D Converter

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Manufacturer	ETC2 [List of Unclassifed Manufacturers]

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KAD5514P

Rev 0.5.1 Preliminary

Page 6

Switching Specifications

Timing Diagrams

Parameter

Symbol

Min

Typ

Max

Units

ADC

Aperture Delay

tA

375

ps

RMS Aperture Jitter

jA

52

fs

Input Clock to Output Clock Propagation Delay

tCPD

TBD

ps

Input Clock to Data Propagation Delay

tPD

TBD

ps

Output Clock to Data Propagation Delay

tDC

TBD

ps

Latency (Pipeline Delay)

L

8.5

cycles

Over Voltage Recovery

tOVR

1

cycles

Figure 1a. LVDS Timing Diagram—DDR

Figure 2a. CMOS Timing Diagram—DDR

Figure 1b. LVDS Timing Diagram—SDR

Figure 2b. CMOS Timing Diagram—SDR

INP

INN

CLKP

CLKN

CLKOUTP

CLKOUTN

D[12/10/8/6/4/2/0]N

D[12/10/8/6/4/2/0]P

tA

tCPD

tDC

tPD

Odd Bits

N-L

Even Bits

N-L

Odd Bits

N-L+1

Even Bits

N-L+1

Latency = L Cycles

Sample N

Odd Bits

N-L+2

Even Bits

N-L+2

Odd Bits

N

INP

INN

CLKP

CLKN

CLKOUT

D[12/10/8/6/4/2/0]

tA

tCPD

tDC

tPD

Odd Bits

N-L

Even Bits

N-L

Odd Bits

N-L+1

Even Bits

N-L+1

Latency = L Cycles

Sample N

Odd Bits

N-L+2

Even Bits

N-L+2

Odd Bits

N

INP

INN

CLKP

CLKN

CLKOUTP

CLKOUTN

D[13:0]N

D[13:0]P

tA

tCPD

tDC

tPD

Data

N-L

Latency = L Cycles

Sample N

Data

N-L+1

Data

N-L+2

Data

N

INP

INN

CLKP

CLKN

CLKOUT

tA

tCPD

tDC

tPD

Latency = L Cycles

Sample N

D[13:0]

Data

N-L

Data

N-L+1

Data

N-L+2

Data

N

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