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KAD5610P
Rev 0.5.1 Preliminary
Page 5
Digital Specifications
Timing Diagrams
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Inputs
Input Current High (RESETN)
IIH
VIN = 1.8V
0
1
10
µA
Input Current Low (RESETN)
IIL
VIN = 0V
25
50
75
µA
Input Current High (OUTMODE,
NAP/SLP, CLKDIV, OUTFMT )
IIH
TBD
25
TBD
µA
Input Current Low (OUTMODE,
NAP/SLP, CLKDIV, OUTFMT )
IIL
TBD
25
TBD
µA
Input Capacitance
CDI
3
pF
LVDS Outputs
Differential Output Voltage
VT
210
mV
Output Rise Time
tR
500
ps
Output Fall Time
tF
500
ps
CMOS Outputs
Voltage Output High
VOH
OVDD-0.1
V
Voltage Output Low
VOL
0.1
V
Output Offset Voltage
VOS
TBD
mV
Output Rise Time
tR
TBD
ns
Output Fall Time
tF
TBD
ns
Figure 1. LVDS Timing Diagram—DDR
Figure 2. CMOS Timing Diagram—DDR
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