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M74HC573F1R Datasheet(PDF) 1 Page - STMicroelectronics |
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M74HC573F1R Datasheet(HTML) 1 Page - STMicroelectronics |
1 / 13 page M54/74HC563 M54/74HC573 October 1993 HC563 INVERTING - HC573 NON INVERTING OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT B1R (Plastic Package) ORDER CODES : M54HCXXXF1R M74HCXXXM1R M74HCXXXB1R M74HCXXXC1R F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) PIN CONNECTION (top view) . HIGH SPEED tPD = 13 ns (TYP.) AT VCC =5 V . LOW POWER DISSIPATION ICC =4 µA (MAX.) AT TA =25 °C . HIGH NOISE IMMUNITY VNIH =VNIL =28 % VCC (MIN.) . OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS . SYMMETRICAL OUTPUT IMPEDANCE IOL = IOH= 6 mA (MIN.) . BALANCED PROPAGATION DELAYS tPLH =tPHL . WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V . PIN AND FUNCTION COMPATIBLE WITH 54/74LS563/573 DESCRIPTION The M54/74HC563 and M54HC573 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C 2MOS technology. These ICs archive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation. These 8 bit D-Type latches are controlled by a latch enable input (LE) and a output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while high level the outpts will be in a high impedance state. The application designer has a choise of combination of inverting and non inverting outputs. The three state output configuration and the wide choise of outline make bus organized system simple. All inputs are equipped with protection circuits against discharge and transient excess voltage. HC563 HC573 HC563 HC573 1/13 |
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