List of Figures
Figure 1-1.
Stellaris® Fury-class High-Level Block Diagram ................................................................ 29
Figure 2-1.
CPU Block Diagram ......................................................................................................... 37
Figure 2-2.
TPIU Block Diagram ........................................................................................................ 38
Figure 5-1.
JTAG Module Block Diagram ............................................................................................ 48
Figure 5-2.
Test Access Port State Machine ....................................................................................... 51
Figure 5-3.
IDCODE Register Format ................................................................................................. 56
Figure 5-4.
BYPASS Register Format ................................................................................................ 57
Figure 5-5.
Boundary Scan Register Format ....................................................................................... 57
Figure 6-1.
External Circuitry to Extend Reset .................................................................................... 59
Figure 7-1.
Hibernation Module Block Diagram ................................................................................. 118
Figure 8-1.
Flash Block Diagram ...................................................................................................... 135
Figure 9-1.
GPIODATA Write Example ............................................................................................. 160
Figure 9-2.
GPIODATA Read Example ............................................................................................. 160
Figure 10-1.
GPTM Module Block Diagram ........................................................................................ 201
Figure 10-2.
16-Bit Input Edge Count Mode Example .......................................................................... 205
Figure 10-3.
16-Bit Input Edge Time Mode Example ........................................................................... 206
Figure 10-4.
16-Bit PWM Mode Example ............................................................................................ 207
Figure 11-1.
WDT Module Block Diagram .......................................................................................... 233
Figure 12-1.
ADC Module Block Diagram ........................................................................................... 257
Figure 12-2.
Internal Temperature Sensor Characteristic ..................................................................... 260
Figure 13-1.
UART Module Block Diagram ......................................................................................... 290
Figure 13-2.
UART Character Frame ................................................................................................. 291
Figure 13-3.
IrDA Data Modulation ..................................................................................................... 293
Figure 14-1.
SSI Module Block Diagram ............................................................................................. 329
Figure 14-2.
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 331
Figure 14-3.
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 332
Figure 14-4.
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 333
Figure 14-5.
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 333
Figure 14-6.
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 334
Figure 14-7.
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 334
Figure 14-8.
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 335
Figure 14-9.
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 336
Figure 14-10. MICROWIRE Frame Format (Single Frame) .................................................................... 336
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 337
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 338
Figure 15-1.
I
2C Block Diagram ......................................................................................................... 363
Figure 15-2.
I
2C Bus Configuration .................................................................................................... 364
Figure 15-3.
START and STOP Conditions ......................................................................................... 364
Figure 15-4.
Complete Data Transfer with a 7-Bit Address ................................................................... 365
Figure 15-5.
R/S Bit in First Byte ........................................................................................................ 365
Figure 15-6.
Data Validity During Bit Transfer on the I
2C Bus ............................................................... 365
Figure 15-7.
Master Single SEND ...................................................................................................... 368
Figure 15-8.
Master Single RECEIVE ................................................................................................. 369
Figure 15-9.
Master Burst SEND ....................................................................................................... 370
Figure 15-10. Master Burst RECEIVE .................................................................................................. 371
Figure 15-11. Master Burst RECEIVE after Burst SEND ........................................................................ 372
9
June 04, 2007
Preliminary
LM3S6965 Microcontroller