MT90502 datasheet(9/191 Pages) ZARLINK

Part #	MT90502

Description	Multi-Channel AAL2 SAR

Download	191 Pages

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Manufacturer	ZARLINK [Zarlink Semiconductor Inc]

Direct Link	http://www.zarlink.com

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9 / 191 page

Preliminary Datasheet

MT90502

9

B9

Z

1. rxa_enb

2. rxa_clav

O

LVTTL 6 mA (F)

1. UTOPIA port A RX Enable in

ATM mode

2. UTOPIA port A RX Cell

Available in PHY mode

C9

1. rxa_clav

2. rxa_enb

I

LVTTL (F)

1. UTOPIA port A RX Cell

Available in ATM mode

2. UTOPIA port A RX Enable in

PHY mode

A12, C11, B11, A11, D10, C10,

B10, A10

rxa_d[7:0]

I

LVTTL (F)

UTOPIA port A RX Data bus

B12

rxa_prty

I

LVTTL (F)

UTOPIA port A RX Parity

D17

Z

txb_led

I/O

LVTTL 12 mA (F)

UTOPIA port B TX LED

C17

Z

rxb_led

I/O

LVTTL 12 mA (F)

UTOPIA port B RX LED

B17

rxb_alarm

I

LVTTL (F)

UTOPIA port B PHY alarm

D5

Z

txb_clk

I/O

LVTTL 6 mA (F)

UTOPIA port B TX clock

D8

Z

txb_soc

O

LVTTL 6 mA (F)

UTOPIA port B TX Start of Cell

A6

Z

1. txb_enb

2. txb_clav

O

LVTTL 6 mA (F)

1. UTOPIA port B TX Enable in

ATM mode

2. UTOPIA port B TX Cell

Available in PHY mode

B6

1. txb_clav

2. txb_enb

I

LVTTL (F)

1. UTOPIA port B TX Cell

Available in ATM mode

2. UTOPIA port B TX Enable in

PHY mode

B8, A8, D7, C7, B7, A7, D6, C6

Z

txb_d[7:0]

O

LVTTL 6 mA (F)

UTOPIA port B TX Data bus

C8

Z

txb_prty

O

LVTTL 6 mA (F)

UTOPIA port B TX Parity

E4

Z

rxb_clk

I/O

LVTTL 6 mA (F)

UTOPIA port B RX clock

A4

1. rxb_soc

2. txa_addr[4]

I

LVTTL (F)

1. UTOPIA port B RX Start of Cell

2. txa_addr[4] when port A and B

are combined

D3

Z

1. rxb_enb

2. rxb_clav

O

LVTTL 6 mA (F)

1. UTOPIA port B RX Enable in

ATM mode

2. UTOPIA port B RX Cell

Available in PHY mode

C1

1. rxb_clav

2. rxb_enb

I

LVTTL (F)

1. UTOPIA port B RX Cell

Available in ATM mode

2. UTOPIA port B RX Enable in

PHY mode

A2, D4, A1, B1, C2

1. rxb_d[4:0]

2. rxa_addr[4:0]

I

LVTTL (F)

1. UTOPIA port B RX Data bus

[4:0]

2. rxa_addr[4:0] when port A and

B are combined

A3, B3, B2

1. rxb_d[7:5]

2. txa_addr[2:0]

I

LVTTL (F)

1. UTOPIA port B RX Data bus

[7:5]

2. txa_addr[2:0] when port A and

B are combined

B4

1. rxb_prty

2. txa_addr[3]

I

LVTTL (F)

1. UTOPIA port B RX Parity.

2. txa_addr[3] when port A and B

are combined.

Pins

rst

Name

I/O

Type

Description

Table 2 - UTOPIA Interface Pins

(continued)

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