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M29W641DU12N1F Datasheet(PDF) 8 Page - STMicroelectronics |
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M29W641DU12N1F Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 42 page M29W641DH, M29W641DL, M29W641DU 8/42 SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A21). The Address Inputs select the cells in the memory array to access dur- ing Bus Read operations. During Bus Write opera- tions they control the commands sent to the Command Interface of the Program/Erase Con- troller. Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ8-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write op- erations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, con- trols the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Com- mand Interface. Write Protect (WP). The Write Protect pin is available in the M29W641DH and M29W641DL only. It provides a hardware method of protecting the highest address block for the M29W641DH and the lowest address block for the M29W641DL. The Write Protect pin must not be left floating or unconnected. When Write Protect is Low, VIL, the memory pro- tects either the highest or lowest address block; Program and Erase operations in this block are ig- nored while Write Protect is Low. When Write Protect is High, VIH, the memory re- verts to the previous protection status for this block. Program and Erase operations can now modify the data in this block unless the block is protected using Block Protection. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy is high-im- pedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy be- comes high-impedance. See Table 13 and Figure 12, Reset/Block Temporary Unprotect AC Charac- teristics. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if Write Protect (WP) is at VIL, then one of the two outermost blocks will remain protected even if RP is at VID. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See Table 13 and Figure 12, Reset/Block Temporary Unprotect AC Characteristics, for more details. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. VPP (VPP). When the VPP pin is raised to VPPH the memory automatically enters the Unlock By- pass mode. When the pin is returned to VIH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the Command Interface section. The transitions from VIH to VPP and from VPP to VIH must be slower than tVHVPP, see Figure 13. Never raise the pin to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. VCC Supply Voltage (2.7V to 3.6V). VCC pro- vides the power supply for all operations (Read, Program and Erase). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from ac- cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. VCCQ Supply Voltage (1.8V to 3.6V). VCCQ pro- vides the power supply to the I/O pins and enables all Outputs to be powered independently of VCC. |
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