Figure 14-12. Master Burst SEND after Burst RECEIVE ........................................................................ 347
Figure 14-13. Slave Command Sequence ............................................................................................ 348
Figure 15-1.
Analog Comparator Module Block Diagram ..................................................................... 373
Figure 15-2.
Structure of Comparator Unit .......................................................................................... 374
Figure 15-3.
Comparator Internal Reference Structure ........................................................................ 375
Figure 16-1.
PWM Module Block Diagram .......................................................................................... 385
Figure 16-2.
PWM Count-Down Mode ................................................................................................ 386
Figure 16-3.
PWM Count-Up/Down Mode .......................................................................................... 387
Figure 16-4.
PWM Generation Example In Count-Up/Down Mode ....................................................... 387
Figure 16-5.
PWM Dead-Band Generator ........................................................................................... 388
Figure 17-1.
QEI Block Diagram ........................................................................................................ 422
Figure 17-2.
Quadrature Encoder and Velocity Predivider Operation .................................................... 423
Figure 18-1.
Pin Connection Diagram ................................................................................................ 438
Figure 21-1.
Load Conditions ............................................................................................................ 458
Figure 21-2.
I2C Timing ..................................................................................................................... 460
Figure 21-3.
Hibernation Module Timing ............................................................................................. 461
Figure 21-4.
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 461
Figure 21-5.
SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 462
Figure 21-6.
SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 462
Figure 21-7.
JTAG Test Clock Input Timing ......................................................................................... 463
Figure 21-8.
JTAG Test Access Port (TAP) Timing .............................................................................. 464
Figure 21-9.
JTAG TRST Timing ........................................................................................................ 464
Figure 21-10. External Reset Timing (RST) .......................................................................................... 465
Figure 21-11. Power-On Reset Timing ................................................................................................. 465
Figure 21-12. Brown-Out Reset Timing ................................................................................................ 465
Figure 21-13. Software Reset Timing ................................................................................................... 466
Figure 21-14. Watchdog Reset Timing ................................................................................................. 466
Figure 22-1.
100-Pin LQFP Package .................................................................................................. 467
9
November 30, 2007
Preliminary
LM3S1960 Microcontroller