Symbol

Parameter

Value

Unit

Ambient Operating Temperature

(3)

–40 to 125

°C

Temperature Under Bias

–50 to 125

°C

Storage Temperature

–65 to 150

°C

(2)

Input or Output Voltages

–0.6 to 7

V

Supply Voltage

–0.6 to 7

V

(2)

A9, E, G, RP Voltage

–0.6 to 13.5

V

Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

3. Depends on range.

graming and erase on programming equipment,

and temporarily unprotected to make changes in

the application.

Instructions for Read/Reset, Auto Select for read-

ing the Electronic Signature or Block Protection

status, Programming, Block and Chip Erase, Erase

Suspend and Resume are written to the device in

cyclesof commands to a CommandInterface using

standard microprocessor write timings.

The device is offered in TSOP48 (12 x 20mm) and

SO44 packages. Both normal and reverse pinouts

are available for the TSOP48 package.

Organisation

The M29F400 is organised as 512K x8 or 256K x16

bits selectable by the BYTE signal. When BYTE is

Low the Byte-wide x8 organisation is selected and

the address lines are DQ15A–1 and A0-A17. The

Data Input/Output signal DQ15A–1 acts as ad-

dress line A–1 which selects the lower or upper

Byte of the memory word for output on DQ0-DQ7,

DQ8-DQ14 remain at High impedance. When

BYTE is High the memory uses the address inputs

A0-A17 and the Data Input/Outputs DQ0-DQ15.

Memory control is provided by Chip Enable E,

Output Enable G and Write Enable W inputs.

A Reset/Block Temporary Unprotection RP tri-level

input provides a hardware reset when pulled Low,

blocks previously protected allowing them to be

programed and erased. Erase and Program opera-

tions are controlled by an internal Program/Erase

Controller (P/E.C.). Status Register data output on

DQ7 provides a Data Polling signal, and DQ6 and

DQ2 provide Toggle signals to indicate the state of

the P/E.C operations. A Ready/Busy RB output

indicates the completion of the internal algorithms.

Memory Blocks

The devices feature asymmetrically blocked archi-

tecture providing system memory integration. Both

M29F400T and M29F400B devices have an array

of 11 blocks, one Boot Block of 16 KBytes or 8

KWords, two Parameter Blocks of 8 KBytes or 4

KWords, one Main Block of 32 KBytes or 16

KWords and seven Main Blocks of 64 KBytes or 32

KWords. The M29F400T has the Boot Block at the

top of the memory address space and the

M29F400B locates the Boot Block starting at the

bottom. The memory maps are showed in Figure

3. Each block can be erased separately, any com-

bination of blocks can be specified for multi-block

erase or the entire chip may be erased. The Erase

operations are managed automatically by the

P/E.C. The block erase operation can be sus-

pended in order to read from or program to any

block not being ersased, and then resumed.

Block protection provides additional data security.

Each block can be separately protected or unpro-

tected against Program or Erase on programming

equipment. All previously protected blocks can be

temporarily unprotected in the application.

Bus Operations

The following operations can be performed using

the appropriate bus cycles: Read (Array, Electronic

Signature, Block Protection Status), Write com-

mand, Output Disable, Standby, Reset, Block Pro-

t ec t i on, Unpr ot ec t ion, Prot ect i on Veri f y,

Unprotection Verify and Block Temporary Unpro-

tection. See Tables 4 and 5.

DESCRIPTION (Cont’d)

3/34

M29F400T, M29F400B