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M48Z512AY-85CS9 Datasheet(PDF) 2 Page - STMicroelectronics |
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M48Z512AY-85CS9 Datasheet(HTML) 2 Page - STMicroelectronics |
2 / 17 page M48Z512A, M48Z512AY 2/17 Figure 2. DIP Connections A1 A0 DQ0 A7 A4 A3 A2 A6 A5 A13 A10 A8 A9 DQ7 A15 A11 G E DQ5 DQ1 DQ2 DQ3 VSS DQ4 DQ6 A16 A18 VCC AI02044 M48Z512A M48Z512AY 10 1 2 5 6 7 8 9 11 12 13 14 15 16 30 29 26 25 24 23 22 21 20 19 18 17 A12 A14 W A17 3 4 28 27 32 31 Table 2. Absolute Maximum Ratings (1) Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260 °C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. Table 3. Operating Modes Note: 1. X = VIH or VIL;VSO = Battery Back-up Switchover Voltage. Symbol Parameter Value Unit TA Ambient Operating Temperature 0 to 70 °C TSTG Storage Temperature (VCC Off) –40 to 70 °C TBIAS Temperature Under Bias –40 to 70 °C TSLD (2) Lead Solder Temperature for 10 seconds 260 °C VIO Input or Output Voltages –0.3 to 7 V VCC Supply Voltage –0.3 to 7 V Mode VCC E G W DQ0-DQ7 Power Deselect 4.75V to 5.5V or 4.5V to 5.5V VIH X X High Z Standby Write VIL XVIL DIN Active Read VIL VIL VIH DOUT Active Read VIL VIH VIH High Z Active Deselect VSO to VPFD (min) X X X High Z CMOS Standby Deselect ≤ VSO X X X High Z Battery Back-up Mode DESCRIPTION The M48Z512A/512AY ZEROPOWER® RAM is a non-volatile 4,194,304 bit Static RAM organized as 524,288 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic 32 pin DIP Module. For surface mount environments ST provides a Chip Set solution consisting of a 28 pin 330mil SOIC NVRAM Supervisor (M40Z300) and a 32 pin TSOP Type II (10 x 20mm) LPSRAM (M68Z512) packages. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC pack- age after the completion of the surface mount pro- cess. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface- mounting. The SNAPHAT housing is keyed to pre- vent reverse insertion. The SNAPHAT battery package is shipped sepa- rately in plastic anti-static tubes or in Tape & Reel form. The part number is ”M4Zxx-BR00SH1”. |
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