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M48Z58-70PC1TR Datasheet(PDF) 7 Page - STMicroelectronics |
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M48Z58-70PC1TR Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 17 page Symbol Parameter M48Z58 / M48Z58Y Unit -70 Min Max tAVAV Write Cycle Time 70 ns tAVWL Address Valid to Write Enable Low 0 ns tAVEL Address Valid to Chip Enable Low 0 ns tWLWH Write Enable Pulse Width 50 ns tELEH Chip Enable Low to Chip Enable High 55 ns tWHAX Write Enable High to Address Transition 0 ns tEHAX Chip Enable High to Address Transition 0 ns tDVWH Input Valid to Write Enable High 30 ns tDVEH Input Valid to Chip Enable High 30 ns tWHDX Write Enable High to Input Transition 5 ns tEHDX Chip Enable High to Input Transition 5 ns tWLQZ (1, 2) Write Enable Low to Output Hi-Z 25 ns tAVWH Address Valid to Write Enable High 60 ns tAVEH Address Valid to Chip Enable High 60 ns tWHQX (1, 2) Write Enable High to Output Transition 5 ns Notes: 1. CL = 5pF (see Figure 4). 2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state. Table 10. Write Mode AC Characteristics (TA = 0 to 70 °C or –40 to 85°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V) READ MODE The M48Z58/58Y is in the Read Mode whenever W (Write Enable) is high, E (Chip Enable) is low. Thus, the unique address specified by the 13 Ad- dress Inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be avail- able at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address In- puts are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. WRITE MODE The M48Z58/58Y is in the Write Mode whenever W and E are low. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Write Enable prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. 7/17 M48Z58, M48Z58Y |
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