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M50LPW116 Datasheet(PDF) 4 Page - STMicroelectronics |
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M50LPW116 Datasheet(HTML) 4 Page - STMicroelectronics |
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4 / 36 page  M50LPW116 4/36 Table 2. Memory Identification Input Configuration Memory Number ID3 ID2 ID1 ID0 A25 A24 A23 A21 1 (Boot) VIL or floating VIL or floating VIL or floating VIL or floating 11 11 2 VIL or floating VIL or floating VIL or floating VIH 11 10 3 VIL or floating VIL or floating VIH VIL or floating 11 01 4 VIL or floating VIL or floating VIH VIH 11 00 5 VIL or floating VIH VIL or floating VIL or floating 10 11 6 VIL or floating VIH VIL or floating VIH 10 10 7 VIL or floating VIH VIH VIL or floating 10 01 8 VIL or floating VIH VIH VIH 10 00 9 VIH VIL or floating VIL or floating VIL or floating 01 11 10 VIH VIL or floating VIL or floating VIH 01 10 11 VIH VIL or floating VIH VIL or floating 01 01 12 VIH VIL or floating VIH VIH 01 00 13 VIH VIH VIL or floating VIL or floating 00 11 14 VIH VIH VIL or floating VIH 00 10 15 VIH VIH VIH VIL or floating 00 01 16 VIH VIH VIH VIH 00 00 Interface Configuration (IC). The Interface Con- figuration input selects whether the Low Pin Count (LPC) or the Address/Address Multiplexed (A/A Mux) Interface is used. The chosen interface must be selected before power-up or during a Reset and, thereafter, cannot be changed. The state of the Interface Configuration, IC, should not be changed during operation. To select the Low Pin Count (LPC) Interface the Interface Configuration pin should be left to float or driven Low, VIL; to select the Address/Address Multiplexed (A/A Mux) Interface the pin should be driven High, VIH. An internal pull-down resistor is included with a value of RIL; there will be a leakage current of ILI2 through each pin when pulled to VIH; see Table 20. Interface Reset (RP). The Interface Reset (RP) input is used to reset the memory. When Interface Reset (RP) is set Low, VIL, the memory is in Reset mode: the outputs are put to high impedance and the current consumption is minimized. When RP is set High, VIH, the memory is in normal operation. After exiting Reset mode, the memory enters Read mode. CPU Reset (INIT). The CPU Reset, INIT, pin is used to Reset the memory when the CPU is reset. It behaves identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical AND) of RP and INIT. Clock (CLK). The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, LAD0-LAD3. The Clock conforms to the PCI specification. Top Block Lock (TBL). The Top Block Lock input is used to prevent the Top Block (Block 49) from being changed. When Top Block Lock, TBL, is set Low, VIL, Program and Block Erase operations in the Top Block have no effect, regardless of the state of the Lock Register. When Top Block Lock, TBL, is set High, VIH, the protection of the Block is determined by the Lock Register. The state of Top Block Lock, TBL, does not affect the protection of the other Blocks (Blocks 0 to 48). Top Block Lock, TBL, must be set prior to a Pro- gram or Block Erase operation is initiated and must not be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing TBL during Program or Erase Suspend. |
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