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M50LPW040N Datasheet(PDF) 3 Page - STMicroelectronics

Part # M50LPW040N
Description  4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M50LPW040N Datasheet(HTML) 3 Page - STMicroelectronics

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M50LPW040
Table 1. Signal Names (LPC Interface) Memory
Note: 1. Pin 9 in the PLCC32, and Pin 21 in the TSOP40, may also
be driven High or driven Low.
LAD0-LAD3
Input/Output Communications
LFRAME
Input Communication Frame
ID0-ID2
Identification Inputs
GPI0-GPI4
General Purpose Inputs
IC
Interface Configuration
RP
Interface Reset
INIT
CPU Reset
CLK
Clock
TBL
Top Block Lock
WP
Write Protect
RFU1
Reserved for Future Use. Leave
disconnected
VCC
Supply Voltage
VPP
Optional Supply Voltage for Fast
Erase Operations
VSS
Ground
NC
Not Connected Internally
Figure 4. PLCC Connections
Note: Pins 27 and 28 are not internally connected.
AI05438
NC
LFRAME
17
ID1
ID0
LAD0
GPI1
TBL
RFU
ID2
GPI0
WP
9
VSS
1
VCC
NC
RFU
32
M50LPW040
IC (VIL)
INIT
RFU
25
A1
A0
DQ0
A7
A4
A3
A2
A6
A5
NC
W
VSS
VCC
NC
DQ7
IC (VIH)
G
RB
A/A Mux
A/A Mux
A/A Mux
A/A Mux
current PC Chipsets; the M50LPW040 acts as the
PC BIOS on the Low Pin Count bus for these PC
Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in TSOP40 (10 x 20mm)
and PLCC32 packages and it is supplied with all
the bits erased (set to ’1’).
SIGNAL DESCRIPTIONS
There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Con-
figuration Pin, IC.
The signals for each interface are discussed in the
Low Pin Count (LPC) Signal Descriptions section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section below. The supply sig-
nals are discussed in the Supply Signal Descrip-
tions section below.


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