M48Z35, M48Z35Y

4/18

The SOIC and battery packages are shipped sep-

arately in plastic anti-static tubes or in Tape & Reel

form.

For the 28 lead SOIC, the battery package (i.e.

SNAPHAT) part number is "M4Z28-BR00SH1".

The M48Z35/35Y also has its own Power-fail De-

tect circuit. The control circuitry constantly moni-

tors the single 5V supply for an out of tolerance

write protects the SRAM, providing a high degree

of data security in the midst of unpredictable sys-

below approximately 3V, the control circuitry con-

nects the battery which maintains data until valid

power returns.

READ MODE

The M48Z35/35Y is in the Read Mode whenever

W (Write Enable) is high, E (Chip Enable) is low.

The device architecture allows ripple-through ac-

cess of data from eight of 264,144 locations in the

static storage array. Thus, the unique address

specified by the 15 Address Inputs defines which

one of the 32,768 bytes of data is to be accessed.

Valid data will be available at the Data I/O pins

address input signal is stable, providing that the E

and G access times are also satisfied. If the E and

G access times are not met, valid data will be

available after the latter of the Chip Enable Access

The state of the eight three-state Data I/O signals

is controlled by E and G. If the outputs are activat-

puts are changed while E and G remain active,

output data will remain valid for Output Data Hold

Address Access.

WRITE MODE

The M48Z35/35Y is in the Write Mode whenever

W and E are low. The start of a write is referenced

from the latter occurring falling edge of W or E. A

write is terminated by the earlier rising edge of W

or E. The addresses must be held valid throughout

the cycle. E or W must return high for a minimum

able prior to the initiation of another read or write

should be kept high during write cycles to avoid

bus contention; although, if the output bus has

been activated by a low on E and G, a low on W

Table 4. AC Measurement Conditions

Note that Output Hi-Z is defined as the point where data is no longer

driven.

Input Rise and Fall Times

≤ 5ns

Input Pulse Voltages

0 to 3V

Input and Output Timing Ref. Voltages

1.5V

Figure 4. AC Testing Load Circuit

AI03211

CL = 100pF or

5pF

CL includes JIG capacitance

645

Ω

DEVICE

UNDER

TEST

1.75V