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M48Z128-70CS1 Datasheet(PDF) 3 Page - STMicroelectronics |
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M48Z128-70CS1 Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 17 page 3/17 M48Z128, M48Z128Y Figure 3. Block Diagram AI01196 INTERNAL BATTERY E VCC VSS VOLTAGE SENSE AND SWITCHING CIRCUITRY 131,072 x 8 SRAM ARRAY A0-A16 DQ0-DQ7 W G POWER E The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC pack- age after the completion of the surface mount pro- cess. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface- mounting. The SNAPHAT housing is keyed to pre- vent reverse insertion. The SNAPHAT battery package is shipped sepa- rately in plastic anti-static tubes or in Tape & Reel form. The part number is ”M4Z28-BRxxSH1”. The M48Z128/128Y also has its own Power-fail Detect circuit. The control circuitry constantly mon- itors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable sys- tem operation brought on by low VCC.As VCC falls below approximately 3V, the control circuitry con- nects the battery which maintains data until valid power returns. READ MODE The M48Z128/128Y is in the Read Mode whenev- er W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 1,048,576 locations in the static storage array. Thus, the unique address specified by the 17 Address Inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G (Output Enable) access times are also sat- isfied. If the E and G access times are not met, val- id data will be available after the later of Chip Enable Access time (tELQV) or Output Enable Ac- cess Time (tGLQV). The state of the eight three- state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain low, output data will remain valid for Output Data Hold time (tAXQX) but will go indeter- minate until the next Address Access. |
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