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M48T59-70MH1 Datasheet(PDF) 9 Page - STMicroelectronics |
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M48T59-70MH1 Datasheet(HTML) 9 Page - STMicroelectronics |
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9 / 21 page  9/21 M48T59, M48T59Y, M48T59V WRITE MODE The M48T59/59Y/59V is in the Write Mode when- ever W and E are low. The start of a write is refer- enced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Write Enable prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX afterward. G should be kept high during write cy- cles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls. DATA RETENTION MODE With valid VCC applied, the M48T59/59Y/59V op- erates as a conventional BYTEWIDE static RAM. Should the supply voltage decay, the RAM will au- tomatically power-fail deselect, write protecting it- self when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high imped- ance, and all inputs are treated as "don’t care." Note: A power failure during a write cycle may cor- rupt data at the currently addressed location, but does not jeopardize the rest of the RAM’s content. At voltages below VPFD (min), the user can be as- sured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T59/59Y/59V may respond to transient noise spikes on VCC that reach into the deselect window Table 11. Register Map Address Data Function/Range BCD Format D7 D6 D5 D4 D3 D2 D1 D0 1FFFh 10 Years Year Year 00-99 1FFEh 0 0 0 10 M Month Month 01-12 1FFDh 0 0 10 Date Date Date 01-31 1FFCh 0 FT CB CEB 0 Day Century/Day 00-01/01-07 1FFBh 0 0 10 Hours Hours Hour 00-23 1FFAh 0 10 Minutes Minutes Minutes 00-59 1FF9h ST 10 Seconds Seconds Seconds 00-59 1FF8h W R S Calibration Control 1FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog 1FF6h AFE Y ABE YYYYY Interrupts 1FF5h RPT4 Y Al. 10 Date Alarm Date Alarm Date 01-31 1FF4h RPT3 Y Al. 10 Hours Alarm Hours Alarm Hours 00-23 1FF3h RPT2 Alarm 10 Minutes Alarm Minutes Alarm Minutes 00-59 1FF2h RPT1 Alarm 10 Seconds Alarm Seconds Alarm Seconds 00-59 1FF1h YYY YYYYY Unused 1FF0h WDF AF Z BL ZZZZ Flags Keys: S = SIGN Bit FT = FREQUENCY TEST Bit R = READ Bit W = WRITE Bit ST = STOP Bit 0 = Must be set to zero Y = ’1’ or ’0’ Z = ’0’ and are Read only AF = Alarm Flag BL = Battery Low WDS = Watchdog Steering Bit BMB0-BMB4 = Watchdog Multiplier Bits RB0-RB1 = Watchdog Resolution Bits AFE = Alarm Flag Enable ABE = Alarm in Battery Back-up Mode Enable RPT1-RPT4 = Alarm Repeat Mode Bits WDF = Watchdog Flag CEB = Century Enable Bit CB = Century Bit |
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