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M48Z512A Datasheet(PDF) 8 Page - STMicroelectronics |
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M48Z512A Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 17 page M48Z512A, M48Z512AY 8/17 Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms Note: Write Enable (W) = High. AI01221 tAVAV tAVQV tAXQX tELQV tELQX tEHQZ tGLQV tGLQX tGHQZ DATA OUT A0-A18 E G DQ0-DQ7 VALID READ MODE The M48Z512A/512AY is in the Read Mode when- ever W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripple- through access of data from eight of 4,194,304 lo- cations in the static storage array. Thus, the unique address specified by the 19 Address Inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, provid- ing that the E (Chip Enable) and G (Output En- able) access times are also satisfied. If the E and G access times are not met, valid data will be available after the later of Chip Enable Access time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Ad- dress Inputs are changed while E and G remain low, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. |
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