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LS7060 Datasheet(PDF) 2 Page - LSI Computer Systems |
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LS7060 Datasheet(HTML) 2 Page - LSI Computer Systems |
2 / 6 page SCAN COUNTER AND DECODER The scan counter is reset to the least significant byte position (State 1) when SCAN RESET input is brought low for a mini- mum of 1µs. The scan counter is enabled for counting as long as the ENABLE input is held low. The counter advances to the next significant byte position on each negative transition of the SCAN pulse. When the scan counter advances to State 5 it dis- ables the Output Drivers and stops in that state until SCAN RESET is again brought low. SCAN When the scan counter is enabled, each negative transition of this input advances the scan counter to its next state. When SCAN is low the Data Outputs are disabled. When SCAN is brought high the Data Outputs are enabled and present the latched counter data corresponding to the present state of the scan counter. Therefore, in microprocessor applications, the Data Output Bus may be utilized for other activities while new data is propagating to the outputs. This positive SCAN pulse can be viewed as a "Place the next byte on my bus" instruction from the microprocessor. Minimum positive and negative pulse widths of 500ns for the SCAN signal are required for scan counter operation. SCAN RESET/LOAD When this input is brought low for a minimum of 1µs, the scan counter is reset to State 1, the least significant byte position, and the latches are simultaneously loaded with new count information. ENABLE When this input is high, the scan counter and the Data Outputs are disabled. When ENABLE is low, the scan counter and Data Out- puts are enabled for normal operation. Transition of this input should only be made while the SCAN input is in a low state in order to prevent false clocking of the scan counter. CASCADE ENABLE This output is normally high. It transitions low and stays low when the scan counter advances to State 5. In a multiple counter system this output is connected to the ENABLE input of the next counter in the cascade string. The SCAN input and SCAN RESET/LOAD in- put are carried to all the counters in the "Cascade". Counter 1 then presents its bytes of data to the Output Bus on each positive transi- tion of the SCAN pulse as previously discussed. When State 5 of Counter 1 is achieved, Counter 2 presents its data to the Output Bus. This sequence continues until all counters in the cascade have been addressed. See Figure 5 for an illustration of a 3 device cascade design. This output is TTL and CMOS compatible. THREE-STATE DATA OUTPUT DRIVERS The eight Data Output Drivers are disabled when either ENABLE input is high, the scan counter is in State 5, or the SCAN input is low. The Output Drivers are TTL and Bus compatible. ABSOLUTE MAXIMUM RATINGS: PARAMETER SYMBOL VALUE UNIT Storage Temperature TSTG -55 to +150 °C Operating Temperature TA 0 to +70 °C Voltage (any pin to VSS) VIN +10 to -0.3 V DC ELECTRICAL CHARACTERISTICS: (VDD = +5V ± 5%, VSS = 0V, TA = 0˚C to +70˚C unless otherwise noted.) PARAMETER SYMBOL Min MAX UNIT CONDITIONS Power Supply Current IDD - 15 mA At Maximum Operating Frequency VDD = Max, Outputs No Load Input High Voltage VIH +3.5 VDD V - Input Low Voltage VIL 0 +0.6 V - Output High Voltage CASCADE ENABLE VOH VDD - 0.2 - V IO = 0, VDD = Min +2.4 - V IO = -100µA, VDD = Min B0 - B7 +2.4 - V IO = -260µA, VDD = Min Output Low Voltage +2.0 - V IO = 750µA, VDD = Min CASCADE ENABLE VOL - +0.2 V IO = 0, VDD = Min +0.4 V IO = 1.6mA, VDD = Min B0 - B7 +0.4 V IO = 1.6mA, VDD = Min Output Source Current Isource 3.0 - mA VO = +1.2V, VDD = Min B0 - B7 Outputs 4.8 - mA VO = +0.8V, VDD = Min 7.3 - mA VO = +0.4V, VDD = Min Output Sink Current Isink 5.7 - mA VO = +1.2V, VDD = Min B0 - B7 Outputs 4.0 - mA VO = +0.8V, VDD = Min 2.2 - mA VO = +0.4V, VDD = Min Output Leakage Current IOL - 1 µA VO = +0.4V to +2.4V,VDD = Min B0 - B7 (Off State) Input Capacitance CIN - 6 pF TA = 25˚C, f = 1MHz Output Capacitance COUT - 12 pF TA = 25˚C, f = 1MHz Input Leakage Current ILI - 1 µA VDD = Max ENABLE, RESET, SCAN 7060-012703-2 The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. |
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