M48Z128, M48Z128Y

8/17

Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms

Note: Write Enable (W) = High.

AI01197

tAVAV

tAVQV

tAXQX

tELQV

tELQX

tEHQZ

tGLQV

tGLQX

tGHQZ

DATA OUT

A0-A16

E

G

DQ0-DQ7

VALID

WRITE MODE

The M48Z128/128Y is in the Write Mode whenev-

er W and E are active. The start of a write is refer-

enced from the latter occurring falling edge of W or

E. A write is terminated by the earlier rising edge

of W or E.

The addresses must be held valid throughout the

of another read or write cycle. Data-in must be val-

high during write cycles to avoid bus contention;

although, if the output bus has been activated by a

low on E and G, a low on W will disable the outputs

DATA RETENTION MODE

Should the supply voltage decay, the RAM will au-

tomatically power-fail deselect, write protecting it-

become high impedance, and all inputs are treated

as ”don’t care.”

If power fail detection occurs during a valid ac-

cess, the memory cycle continues to completion. If

the memory cycle fails to terminate within the time

the internal energy source which preserves data.

The internal coin cell will maintain data in the

for an accumulated period of at least 10 years

connected, and the power supply is switched to

resume.

For more information on Battery Storage Life refer

to the Application Note AN1012.