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M48T37V-10MH1E Datasheet(PDF) 7 Page - STMicroelectronics |
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M48T37V-10MH1E Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 29 page  7/29 M48T37Y, M48T37V OPERATION MODES As Figure 4., page 6 shows, the static memory ar- ray and the quartz controlled clock oscillator of the M48T37Y/V are integrated on one silicon chip. The memory locations that provide user accessi- ble BYTEWIDE™ clock information are in the bytes with addresses 7FF1 and 7FF9h-7FFFh (lo- cated in Table 5., page 13). The clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour BCD format. Cor- rections for 28, 29 (leap year - valid until the year 2100), 30, and 31 day months are made automat- ically. Byte 7FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. Byte 7FF7h contains the watchdog timer setting. The watchdog timer redirects an out-of-control mi- croprocessor and provides a reset or interrupt to it. Bytes 7FF2h-7FF5h are reserved for clock alarm programming. These bytes can be used to set the alarm. This will generate an active low signal on the IRQ/FT pin when the alarm bytes match the date, hours, minutes, and seconds of the clock. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE memory cells. The M48T37Y/V includes a clock control cir- cuit which updates the clock bytes with current in- formation once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T37Y/V also has its own Power-fail De- tect circuit. The control circuitry constantly moni- tors the single VCC supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable sys- tem operation brought on by low VCC. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until val- id power returns. Table 2. Operating Modes Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 13., page 23 for details. Mode VCC E G W DQ0-DQ7 Power Deselect 4.5 to 5.5V or 3.0 to 3.6V VIH X X High Z Standby WRITE VIL X VIL DIN Active READ VIL VIL VIH DOUT Active READ VIL VIH VIH High Z Active Deselect VSO to VPFD (min) (1) X X X High Z CMOS Standby Deselect ≤ VSO(1) X X X High Z Battery Back-up Mode |
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