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M48T559YMH1TR Datasheet(PDF) 3 Page - STMicroelectronics |
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M48T559YMH1TR Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 18 page 3/18 M48T559Y mation once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T559Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condi- tion. Table 3. Operating Modes (1) Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 2. See Table 7 for details. 3. AD0-AD7, AS0, AS1 active when E is high and VCC > VPFD. Mode VCC E R W AD0-AD7 Power Deselect 4.5V to 5.5V VIH X X High Z Standby (3) Write VIL VIH VIL DIN Active Read VIL VIL VIH DOUT Active Read VIL VIH VIH High Z Active Deselect VSO to VPFD (min) (2) X X X High Z CMOS Standby Deselect ≤ VSO X X X High Z Battery Back-up Mode Figure 3. Block Diagram AI01676B LITHIUM CELL OSCILLATOR AND CLOCK CHAIN VPFD VCC 32,768 Hz CRYSTAL VOLTAGE SENSE AND SWITCHING CIRCUITRY 8176 x 8 SRAM ARRAY W R POWER AS1 AD0-AD7 AS0 RSTIN1 RSTIN2 RST IRQ/FT 16 x 8 BiPORT SRAM ARRAY E VSS DATA TRANSCEIVER UPPER ADDRESS LATCH LOWER ADDRESS LATCH When VCC is out of tolerance, the circuit write pro- tects the SRAM, providing a high degree of data security in the midst of unpredictable system oper- ation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data and clock opera- tion until valid power returns. |
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