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M48T212V-70MH6 Datasheet(PDF) 10 Page - STMicroelectronics |
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M48T212V-70MH6 Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 32 page  M48T212Y, M48T212V 10/32 READ Mode The M48T212Y/V executes a READ cycle when- ever W (WRITE Enable) is high and E (Chip En- able) is low. The unique address specified by the address inputs (A3-A0) defines which one of the on-chip TIMEKEEPER® registers is to be access- ed. When the address presented to the M48T212Y/V is in the range of 0h-Fh, one of the on-board TIMEKEEPER registers is accessed and valid data will be available to the eight data output drivers within tAVQV after the address input signal is stable, providing that the E and G access times are also satisfied.If they are not, then data access must be measured from the latter occurring signal (E or G) and the limiting parameter is either tELQV for E or tGLQV for G rather than the address access time. When EX input is low, an external SRAM location will be selected. Note: Care should be taken to avoid taking both E and EX low simultaneously to avoid bus conten- tion. Figure 6. READ Cycle Timing: RTC Control Signal Waveforms Note: EX is assumed High. Table 5. READ Mode AC Characteristics Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 5pF. Symbol Parameter(1) M48T212Y M48T212V Unit –70 –85 Min Max Min Max tAVAV Read Cycle Time 70 85 ns tAVQV Address Valid to Output Valid 70 85 ns tELQV Chip Enable Low to Output Valid 70 85 ns tGLQV Output Enable Low to Output Valid 25 35 ns tELQX (2) Chip Enable Low to Output Transition 5 5 ns tGLQX (2) Output Enable Low to Output Transition 0 0 ns tEHQZ (2) Chip Enable High to Output Hi-Z 20 25 ns tGHQZ (2) Output Enable High to Output Hi-Z 20 25 ns tAXQX Address Transition to Output Transition 5 5 ns AI02640 W DQ7-DQ0 G DATA OUT VALID ADDRESS tAVAV E tELQV tAVAV tAVAV READ READ WRITE DATA IN VALID DATA OUT VALID tAVQV tWHAX tAVWL tELQX tGLQV tGHQZ tWLWH tAXQX tGLQX |
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