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MPD78CP18GQ-36 Datasheet(PDF) 8 Page - NEC |
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MPD78CP18GQ-36 Datasheet(HTML) 8 Page - NEC |
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8 / 373 page  – i – TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION ........................................................................................... 1 1.1 Features ............................................................................................................................. 3 1.2 Ordering Information and Quality Grade ..................................................................... 5 1.2.1 Ordering information ........................................................................................................... 5 1.2.2 Quality grade ........................................................................................................................ 9 1.3 Pin Configurations (Top View) ....................................................................................... 10 1.3.1 Shrink DIP, QUIP (straight) (37), QUIP (36) ........................................................................ 10 1.3.2 QFP (1B/3BE), WQFN ......................................................................................................... 13 1.3.3 QFP (AB8) ............................................................................................................................ 15 1.3.4 QFJ ....................................................................................................................................... 16 1.4 Block Diagram................................................................................................................... 18 1.5 Functional Comparison of 87AD Series CMOS Products ........................................... 19 1.6 Differences between 87AD Series CMOS and NMOS Products ................................ 21 1.7 Differences between "Standard" and "Special" Quality Grade Products ............... 22 CHAPTER 2 PIN FUNCTIONS ......................................................................................................... 23 2.1 Normal Operation Mode ................................................................................................. 23 2.1.1 PA7 to PA0 (Port A) ............................................................................................................. 23 2.1.2 PB7 to PB0 (Port B) ............................................................................................................. 23 2.1.3 PC7 to PC0 (Port C) ............................................................................................................. 23 2.1.4 PD7 to PD0 (Port D) ............................................................................................................ 25 2.1.5 PF7 to PF0 (Port F) .............................................................................................................. 26 2.1.6 WR (Write strobe) ............................................................................................................... 27 2.1.7 RD (Read strobe) ................................................................................................................. 27 2.1.8 ALE (Address latch enable) ................................................................................................. 27 2.1.9 MODE0, MODE1 (Mode) .................................................................................................... 28 2.1.10 NMI (Non maskable interrupt) ............................................................................................ 28 2.1.11 INT1 (Interrupt request) ...................................................................................................... 28 2.1.12 AN7 to AN0 (Analog input) ................................................................................................. 28 2.1.13 VAREF (Reference voltage) .................................................................................................... 28 2.1.14 AVDD (Analog VDD) ................................................................................................................ 28 2.1.15 AVSS (Analog VSS) ................................................................................................................. 29 2.1.16 STOP (Stop control input) ................................................................................................... 29 2.1.17 X1, X2 (Crystal) .................................................................................................................... 29 2.1.18 RESET (Reset) ..................................................................................................................... 29 2.1.19 VDD ........................................................................................................................................ 29 2.1.20 VSS ........................................................................................................................................ 29 2.1.21 IC .......................................................................................................................................... 29 2.2 EPROM Mode .................................................................................................................... 30 2.2.1 A14 to A0 (Address) ............................................................................................................ 30 2.2.2 O7 to O0 (Data) ................................................................................................................... 30 2.2.3 CE (Chip enable) .................................................................................................................. 30 |
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