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M48T12-200PC1 Datasheet(PDF) 7 Page - STMicroelectronics |
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M48T12-200PC1 Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 15 page  Symbol Parameter M48T02 / M48T12 Unit -70 -150 -200 Min Max Min Max Min Max tAVAV Write Cycle Time 70 150 200 ns tAVWL Address Valid to Write Enable Low 0 0 0 ns tAVEL Address Valid to Chip Enable Low 0 0 0 ns tWLWH Write Enable Pulse Width 50 90 120 ns tELEH Chip Enable Low to Chip Enable High 55 90 120 ns tWHAX Write Enable High to Address Transition 0 10 10 ns tEHAX Chip Enable High to Address Transition 0 10 10 ns tDVWH Input Valid to Write Enable High 30 40 60 ns tDVEH Input Valid to Chip Enable High 30 40 60 ns tWHDX Write Enable High to Input Transition 5 5 5 ns tEHDX Chip Enable High to Input Transition 5 5 5 ns tWLQZ Write Enable Low to Output Hi-Z 25 50 60 ns tAVWH Address Valid to Write Enable High 60 120 140 ns tAVEH Address Valid to Chip Enable High 60 120 140 ns tWHQX Write Enable High to Output Transition 5 10 10 ns Table 10. Write Mode AC Characteristics (TA = 0 to 70 °C; VCC = 4.75V to 5.5V or 4.5V to 5.5V) READ MODE The M48T02/12 is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through ac- cess of data from eight of 16,384 locations in the static storage array. Thus, the unique address specified by the 11 Address Inputs defines which one of the 2,048 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address In- puts are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access. WRITE MODE The M48T02/12 is in the Write Mode whenever W and E are active. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Write Enableprior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX afterward. G shouldbe kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls. 7/15 M48T02, M48T12 |
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