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M41T81MY6TR Datasheet(PDF) 11 Page - STMicroelectronics |
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M41T81MY6TR Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 27 page 11/28 M41T81 Figure 12. Bus Timing Requirements Sequence Table 7. AC Characteristics Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL. Sym Parameter(1) Min Typ Max Units fSCL SCL Clock Frequency 0 400 kHz tLOW Clock Low Period 1.3 µs tHIGH Clock High Period 600 ns tR SDA and SCL Rise Time 300 ns tF SDA and SCL Fall Time 300 ns tHD:STA START Condition Hold Time (after this period the first clock pulse is generated) 600 ns tSU:STA START Condition Setup Time (only relevant for a repeated start condition) 600 ns tSU:DAT (2) Data Setup Time 100 ns tHD:DAT Data Hold Time 0 µs tSU:STO STOP Condition Setup Time 600 ns tBUF Time the bus must be free before a new transmission can start 1.3 µs AI00589 SDA P tSU:STO tSU:STA tHD:STA SR SCL tSU:DAT tF tHD:DAT tR tHIGH tLOW tHD:STA tBUF S P |
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