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M48T02-70PC1 Datasheet(PDF) 9 Page - STMicroelectronics |
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M48T02-70PC1 Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 15 page DATA RETENTION MODE With valid VCC applied, the M48T02/12 operates as a conventionalBYTEWIDE static RAM. Should the supply voltage decay, the RAM will automatically power-faildeselect,write protectingitself when VCC falls within the VPFD(max), VPFD(min) window. All outputsbecome high impedance, and all inputs are treated as ”don’t care.” Note: A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM’s content.At voltagesbelow VPFD(min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T02/12 may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. There- fore, decoupling of the power supply lines is rec- ommended. The power switching circuit connects external VCC to the RAM and disconnects the battery when VCC rises above VSO.As VCC rises, the battery voltage is checked. If the voltage is too low, an internal Battery Not OK (BOK) flag will be set. The BOKflag can be checked after power up. If the BOK flag is set, the first write attempted will be blocked. The flag is automatically cleared after the first write, and normal RAM operation resumes. Figure 9 illus- trates how a BOK check routine could be struc- tured. For more information on a Battery Storage Life refer to the Application Note AN1012. CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. Because the BiPORT TIME- KEEPER cells in the RAM array are only data registers, and not the actual clock counters, updat- ing the registers can be halted without disturbing the clock itself. Updatingis halted when a ’1’ is written to the READ bit, the seventh bit in the control register. As long as a ’1’ remains in that position, updating is halted. After a halt is issued, the registersreflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated si- multaneously. A halt will not interrupt an update in progress.Updating is withina secondafter the read bit is reset to a ’0’. Setting the Clock The eighth bit of the control register is the WRITE bit. Setting the WRITE bit to a ’1’, like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 10). Resetting the WRITE bit to a ’0’ then transfers the values of all time registers (7F9h-7FFh) to the actual TIMEKEEPER counters and allows normal operationto resume.The FT bit and the bits marked as ’0’ in Table 10 must be written to ’0’ to allow for normal TIMEKEEPER and RAM operation. See the Application Note AN923 ”TIMEKEEPER rolling into the 21st century” for more information on Century Rollover. READ DATA AT ANY ADDRESS AI00607 IS DATA COMPLEMENT OF FIRST READ? (BATTERY OK) POWER-UP YES NO WRITE DATA COMPLEMENT BACK TO SAME ADDRESS READ DATA AT SAME ADDRESS AGAIN NOTIFY SYSTEM OF LOW BATTERY (DATA MAY BE CORRUPTED) WRITE ORIGINAL DATA BACK TO SAME ADDRESS (BATTERY LOW) CONTINUE Figure 9. Checking the BOK Flag Status 9/15 M48T02, M48T12 |
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