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M36W108AB100ZM6T Datasheet(PDF) 4 Page - STMicroelectronics |
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M36W108AB100ZM6T Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 36 page M36W108AT, M36W108AB 4/36 Reset Input (RP). The Reset input provides hardware reset of the Flash chip. Reset of the Flash memory is achieved by pulling RP to VIL for at least tPLPX. When the reset pulse is given, if the Flash memory is in Read or Standby modes, it will be available for new operations in tPHEL after the rising edge of RP. If the Flash memory is in Erase or Program mode the reset will take tPLYH during which the Ready/ Busy (RB) signal will be held at VIL. The end of the Flash memory reset will be indicated by the rising edge of RB. A hardware reset during an Erase or Program operation will corrupt the data being pro- grammed or the block(s) being erased. See Table 18 and Figure 10. Ready/Busy Output (RB). Ready/Busy is an open-drain output of the Flash chip. It gives the in- ternal state of the Program/Erase Controller (P/ E.C.) of the Flash device. When RB is Low, the Flash device is busy with a Program or Erase op- eration and it will not accept any additional pro- gram or erase instructions except the Erase Suspend instruction. When RB is High, the Flash device is ready for any Read, Program or Erase operation. The RB will also be High when the Flash memory is put in Erase Suspend or Standby modes. VCCF Supply Voltage. Flash memory power sup- ply for all operations (Read, Program and Erase). VCCS Supply Voltage. SRAM power supply for all operations (Read, Program). VSS Ground. VSS is the reference for all voltage measurements. POWER SUPPLY Power Up. The Flash memory Command Inter- face is reset on power up to Read Array. Either Flash Chip Enable (EF) or Write Enable (W) inputs must be tied to VIH during Power Up to allow max- imum security and the possibility to write a com- mand on the first rising edge of EF and W. Any write cycle initiation is blocked when VCCF is below VLKO. Supply Rails. Normal precautions must be taken for supply voltage decoupling; each device in a system should have the VCCF, VCCS rails decou- pled with a 0.1µF capacitor close to the VCCF, VCCS and VSS pins. The PCB trace widths should be sufficient to carry the VCCF and VCCS program currents and the VCCF erase current required. Table 3. Main Operation Modes (1) Note: 1. X = VIL or VIH. Operation Mode EF E1S E2S G W RP DQ7-DQ0 Flash Chip Read VIL VIH X VIL VIH VIH Data Output VIL X VIL VIL VIH VIH Data Output SRAM Chip Read VIH VIL VIH VIL VIH X Data Output Flash Chip Write VIL VIH X VIH VIL VIH Data Input VIL X VIL VIH VIL VIH Data Input SRAM Chip Write VIH VIL VIH X VIL X Data Input Flash Chip Output Disable X VIH X VIH VIH XHi-Z XX VIL VIH VIH XHi-Z SRAM Chip Output Disable VIH VIL VIH VIH VIH XHi-Z Flash Chip Stand-by VIH XX XX VIH Hi-Z Flash Chip Reset X VIH XX X VIL Hi-Z XX VIL XX VIL Hi-Z SRAM Chip Stand-by X VIH XX X VIL Hi-Z XX VIL XX VIL Hi-Z |
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