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M29W040-200K6R Datasheet(PDF) 5 Page - STMicroelectronics |
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M29W040-200K6R Datasheet(HTML) 5 Page - STMicroelectronics |
5 / 31 page Mne. Instr. Cyc. 1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc. RST (3,9) Read Array/ Reset 1+ Addr. (2,6) X Read Memory Array until a new write cycle is initiated. Data F0h 3+ Addr. (2,6) 5555h 2AAAh 5555h Read Memory Array until a new write cycle is initiated. Data AAh 55h F0h RSIG (3) Read Electronic Signature 3+ Addr. (2,6) 5555h 2AAAh 5555h Read Electronic Signature until a new write cycle is initiated. See Note 4. Data AAh 55h 90h RBP (3) Read Block Protection 3+ Addr. (2,6) 5555h 2AAAh 5555h Read Block Protection until a new write cycle is initiated. See Note 5. Data AAh 55h 90h PG Program 4 Addr. (2,6) 5555h 2AAAh 5555h Program Address Read Data Polling or Toggle Bit until Program completes. Data AAh 55h A0h Program Data BE Block Erase 6 Addr. (2,6) 5555h 2AAAh 5555h 5555h 2AAAh Block Address Additional Block (7) Data AAh 55h 80h AAh 55h 30h 30h CE Chip Erase 6 Addr. (2,6) 5555h 2AAAh 5555h 5555h 2AAAh 5555h Note 8 Data AAh 55h 80h AAh 55h 10h ES Erase Suspend 1 Addr. (2,6) X Read until Toggle stops, then read all the data needed from any uniform block(s) not being erased then Resume Erase. Data B0h ER Erase Resume 1 Addr. (2,6) X Read Data Polling or Toggle Bit until Erase completes or Erase is suspended another time Data 30h PD (10) Power Down 1 Addr. (2,6) 5555h Puts the memory in Power Down mode where power consumption is reduced to typically less than 1 µA Data 20h Notes: 1. Command not interpreted in this table will default to read array mode. 2. X = Don’t Care. 3. The first cycle of the RST, RBP or RSIG instruction is followed by read operations to read memory array, Status Register or Electronic Signature codes. Any number of read cycles can occur after one command cycle. 4. Signature Address bits A0, A1, A6 at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, A6 at VIL will output Device code. 5. Protection Address: A0, A6 at VIL,A1 at VIH and A16, A17, A18 within the uniform block to be checked, will output the Block Protection status. 6. Address bits A15-A18 are don’t care for coded address inputs. 7. Optional, additional blocks addresses must be entered within a 80 µs delay after last write entry, timeout status can be verified through DQ3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended. 8. Read Data Polling or Toggle bit until Erase completes. 9. A wait time of 5 µs is necessary after a Reset command, if the memory is in a Block Erase or Power Down status, before starting any operation. 10. Writing an RST command to the P/E.C. is mandatory prior to any new operation when the memory is in Power Down mode. Table 6. Instructions (1) 5/31 M29W040 |
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