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M29W040-120N1R Datasheet(PDF) 10 Page - STMicroelectronics |
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M29W040-120N1R Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 31 page Symbol Alt Parameter Test Condition M29W040 Unit -100 -120 VCC = 3.3V ±0.3V CL = 30pF VCC = 3.3V ±0.3V Min Max Min Max tAVAV tRC Address Valid to Next Address Valid E = VIL,G= VIL 100 120 ns tAVQV tACC Address Valid to Output Valid E = VIL,G= VIL 100 120 ns tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL 00 ns tELQV (2) tCE Chip Enable Low to Output Valid G = VIL 100 120 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E= VIL 00 ns tGLQV (2) tOE Output Enable Low to Output Valid E = VIL 40 50 ns tEHQX tOH Chip Enable High to Output Transition G= VIL 00 ns tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL 20 30 ns tGHQX tOH Output Enable High to Output Transition E= VIL 00 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL 20 30 ns tAXQX tOH Address Transition to Output Transition E=VIL,G= VIL 00 ns Notes: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV -tGLQV after the falling edge of E without increasing tELQV. Table 12A. Read AC Characteristics (TA = 0 to 70 °C, –20 to 85°C or –40 to 85°C) Toggle bit (DQ6). When Programming operations are in progress, successive attempts to read DQ6 will output complementary data. DQ6 will toggle following toggling of either G or E when G is low. The operation is completed when two successive reads yield the same output data. The next read will output the bit last programmed or a ’1’ after erasing. The toggle bit is valid only effective during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. If the byte to be programmed belongs to a protected block the command will be ignored. If the blocks selected for erasure are protected, DQ6 will toggle for about 100 µs and then return back to Read. See Figure 11 for Toggle Bit flowchart and Figure 12 for Toggle Bit waveforms. Error bit (DQ5). This bit is set to ’1’ by the P/E.C when there is a failure of byte programming, block erase, or chip erase that results in invalid data being programmedin the memory block. In case of error in block erase or byte program, the block in which the error occured or to which the pro- grammed byte belongs, must be discarded. Other blocks may still be used. Error bit resets after Reset (RST) instruction. In case of success, the error bit will set to ’0’ during Program or Erase and to valid data after write operation is completed. Erase Timer bit (DQ3). This bit is set to ’0’ by the P/E.C. when the last Block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the erase timeout period is finished, after 80 to 120 µs, DQ3 returns back to ’1’. Coded Cycles. The two coded cycles unlock the Command Interface. They are followed by a com- mand input or a comand confirmation. The coded cycles consist of writing the data AAh at address 5555h during the first cycle and data 55h at address 2AAAh during the second cycle. Addresses are latched on the falling edge of W or E while data is latched on the rising edge of W or E. The coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles. 10/31 M29W040 |
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