MAX1361_06 datasheet(5/24 Pages) MAXIM

Part #	MAX1361

Description	4-Channel, 10-Bit, System Monitors with Programmable Trip Window and SMBus Alert Response

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Manufacturer	MAXIM [Maxim Integrated Products]

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4-Channel, 10-Bit, System Monitor with Programmable

Trip Window and SMBus Alert Response

_______________________________________________________________________________________

5

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 2.7V to 3.6V (MAX1361), VDD = 4.5V to 5.5V (MAX1362), VREF = 2.048V (MAX1361), VREF = 4.096V (MAX1362), CREF =

0.1µF, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Hold Time for START (S)

Condition

tHD, STA

0.6

µs

Low Period of the SCL Clock

tLOW

1.3

µs

High Period of the SCL Clock

tHIGH

0.6

µs

Setup Time for a Repeated

START Condition (Sr)

tSU, STA

0.6

µs

Data Hold Time

tHD, DAT

0

900

ns

Data Setup Time

tSU, DAT

100

ns

Rise Time of Both SDA and SCL

Signals, Receiving

tR

Measured from 0.3VDD to 0.7VDD

0

300

ns

Fall Time of SDA Transmitting

tF

Measured from 0.3VDD to 0.7VDD

0

300

ns

Setup Time for STOP (P)

Condition

tSU, STO

0.6

µs

Capacitive Load for Each Bus

Line

CB

400

pF

Pulse Width of Spike Suppressed

50

ns

TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Figures 1a, 2) (Note 12)

Serial Clock Frequency

fSCLH

(Note 13)

1.7

MHz

Hold Time, Repeated START

Condition (Sr)

tHD, STA

160

ns

Low Period of the SCL Clock

tLOW

(Note 13)

320

ns

High Period of the SCL Clock

tHIGH

120

ns

Setup Time for a Repeated

START Condition (Sr)

tSU, STA

160

ns

Data Hold Time

tHD, DAT

(Note 14)

0

150

ns

Data Setup Time

tSU, DAT

10

ns

Rise Time of SCL Signal

tRCL

Measured from 0.3VDD to 0.7VDD

20

80

ns

Rise Time of SCL Signal After

Acknowledge Bit

tRCL1

Measured from 0.3VDD to 0.7VDD

20

160

ns

Fall Time of SCL Signal

tFCL

Measured from 0.3VDD to 0.7VDD

20

80

ns

Rise Time of SDA Signal

tRDA

Measured from 0.3VDD to 0.7VDD

20

160

ns

Fall Time of SDA Signal

tFDA

Measured from 0.3VDD to 0.7VDD

20

160

ns

Setup Time for STOP (P)

Condition

tSU, STO

160

ns

Capacitive Load for Each Bus

CB

400

pF

Pulse Width of Spike Suppressed

010

ns

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