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HM5216805TT-12 Datasheet(PDF) 10 Page - Hitachi Semiconductor |
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HM5216805TT-12 Datasheet(HTML) 10 Page - Hitachi Semiconductor |
10 / 60 page HM5216805 Series, HM5216405 Series 10 Command Operation Command Truth Table The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins. CKE Function Symbol n – 1 n CS RAS CAS WE A11 A10 A0 to A9 Ignore command DESL H × H ×××××× No operation NOP H × L HHH ××× Burst stop in full page BST H × L HHL ××× Column address and read command READ H × LH LH V L V Read with auto-precharge READ A H × LH LH V H V Column address and write command WRIT H × LH LLV LV Write with auto-precharge WRIT A H × LH LLV H V Row address strobe and bank act. ACTV H × L L H H VVV Precharge select bank PRE H × LLH LV L × Precharge all bank PALL H × LLH L × H × Refresh REF/SELF H V LLLH ××× Mode register set MRS H × LLLLV V V Note: H: V IH. L: V IL. ×: VIH or VIL. V: Valid address input Ignore command [DESL]: When this command is set (CS is High), the synchronous DRAM ignore command input at the clock. However, the internal status is held. No operation [NOP]: This command is not an execution command. However, the internal operations continue. Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page (512; HM5216805 Series, 1024; HM5216405 Series)), and is illegal otherwise. Full page burst continues until this command is input. When data input/output is completed for a full-page of data, it automatically returns to the start address, and input/output is performed repeatedly. Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address (AY0 to AY8; HM5216805 Series, AY0 to AY9; HM5216405 Series) and the bank select address (BS). After the read operation, the output buffer becomes High-Z. |
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