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M295V800AB70M6T Datasheet(PDF) 5 Page - STMicroelectronics |
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M295V800AB70M6T Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 21 page  5/21 M29F800AT, M29F800AB Table 4A. Bus Operations, BYTE = VIL Note: X = VIL or VIH. Table 4B. Bus Operations, BYTE = VIH Note: X = VIL or VIH. Operation E G W Address Inputs DQ15A–1, A0-A18 Data Inputs/Outpu ts DQ14-DQ8 DQ7-DQ0 Bus Read VIL VIL VIH Cell Address Hi-Z Data Output Bus Write VIL VIH VIL Command Address Hi-Z Data Input Output Disable X VIH VIH X Hi-Z Hi-Z Standby VIH X X X Hi-Z Hi-Z Read Manufacturer Code VIL VIL VIH A0 = VIL,A1 = VIL,A9 = VID, Others VIL or VIH Hi-Z 20h Read Device Code VIL VIL VIH A0 = VIH,A1 = VIL,A9 = VID, Others VIL or VIH Hi-Z ECh (M29F800AT) 58h (M29F800AB) Operation E G W Address Inputs A0-A18 Data Inputs/Outpu ts DQ15A–1, DQ14-DQ0 Bus Read VIL VIL VIH Cell Address Data Output Bus Write VIL VIH VIL Command Address Data Input Output Disable X VIH VIH X Hi-Z Standby VIH X X X Hi-Z Read Manufacturer Code VIL VIL VIH A0 = VIL,A1 = VIL,A9 = VID, Others VIL or VIH 0020h Read Device Code VIL VIL VIH A0 = VIH,A1 = VIL,A9 = VID, Others VIL or VIH 00ECh (M29F800AT) 0058h (M29F800AB) VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Pro- gram, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from ac- cidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. A 0.1 µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC4. VSS Ground. The VSS Ground is the reference for all voltage measurements. BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby and Automatic Standby. See Tables 4A and 4B, Bus Operations, for a summa- ry. Typically glitches of less than 5ns on Chip En- able or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Com- mand Interface. A valid Bus Read operation in- volves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 7, Read Mode AC Waveforms, and Table 11, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Ad- |
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